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WM8961GEFL/V 데이터시트(PDF) 87 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V 데이터시트(HTML) 87 Page - Wolfson Microelectronics plc |
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87 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 87 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1000 = Reserved 1001 = SYSCLK / 12 1010 = SYSCLK / 16 1011 = SYSCLK / 24 1100 = Reserved 1101 to 1111 = SYSCLK / 32 Register 08h Clocking2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 (09h) Audio Interface 1 4:3 DACCOMP[1:0] 00 DAC data companding mode 00 : off 01 : reserved 10 : μ-law 11 : A-law 2:1 ADCCOMP[1:0] 00 ADC data companding mode 00 : off 01 : reserved 10 : μ-law 11 : A-law 0 LOOPBACK 0 Audio interface loopback mode enable 0 : No loopback 1 : Loopback enabled, ADC data output is fed directly into DAC data input Register 09h Audio Interface 1 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R10 (0Ah) Left DAC volume 8 DACVU 0 DAC digital volume update Writing 1 to this bit will cause left and right DAC volumes to be updated (LDACVOL and RDACVOL) 7:0 LDACVOL[7:0] 1111_1111 Left DAC digital volume FFh -> C0h : 0dB BFh : -0.375dB Beh: -0.75dB ….. in steps of -0.375dB to 02h: -71.25dB 01h: -71.625dB 00h: Digital Mute Register 0Ah Left DAC volume |
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