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WM8961GEFL/V 데이터시트(PDF) 67 Page - Wolfson Microelectronics plc

부품명 WM8961GEFL/V
상세설명  Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers
PDF  116 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8961GEFL/V 데이터시트(HTML) 67 Page - Wolfson Microelectronics plc

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WM8961
Pre-Production
w
PP, August 2009, Rev 3.1
67
The default values of the write control sequencer are given in Table 50
WSEQ
_LOCATION
WM8961
REG
_INDEX
EOS
WIDTH
START
DATA
DELAY
COMMENT
CUMULATIVE
DELAY
STARTUP
TIME
0
8’h08
1’b0
3’h0
4’h4
8’h1
4’h0
CLK_DSP_ENA = 1
0.0005
0.0005
1
8’hFE
1’b0
3’h0
4’h0
8’h0
4’h0
Dummy Write for
expansion
0.0005
0.0010
2
8’h1C
1’b0
3’h1
4’h3
8’h3
4’h0
BUFDCOPEN = 1,
BUFIOEN = 1 ; Enable
current bias circuits
0.0005
0.0015
3
8’h19
1’b0
3’h2
4’h6
8’h3
4’h0
VMIDSEL = 01, VREF
= 1 ; VMID can be
brought up fast,
master bias enable
0.0005
0.0020
4
8’h48
1’b0
3’h0
4’h0
8’h01
4’h6
Enable Charge pump,
wait 4.5ms
0.0045
0.0065
5
8’h1A
1’b0
3’h3
4’h5
8’hF
4’h0
LOUT1_PGA = 1,
ROUT1_PGA = 1,
DACL = 1, DACR = 1
0.0005
0.0070
6
8’h45
1’b0
3’h4
4’h0
8’h11
4’h0
Set HPL_ENA,
HPR_ENA
0.0005
0.0075
7
8’h45
1’b0
3’h4
4’h1
8’h19
4’h0
Set HPL_EN_DLY,
HPR_EN_DLY
0.0005
0.0080
8
8’h02
1’b0
3’h6
4’h0
8’h65
4’h0
LOUT1VOL to -20dB
(7’b1100101)
0.0005
0.0085
9
8’h03
1’b0
3’h6
4’h0
8’h65
4’h0
ROUT1VOL to -20dB
(7’b1100101)
0.0005
0.0090
10
8’h03
1’b0
3’h0
4’h8
8’h01
4’h0
OUT1VU
0.0005
0.0095
11
8’h3D
1’b0
3’h5
4’h2
8’h33
4’hC
Enable Servo on
outputs, trigger
startup, wait 256ms
0.2560
0.2655
12
8’hFE
1’b0
3’h0
4’h0
8’h0
4’h0
Dummy Write for
expansion
0.0005
0.2660
13
8’h07
1’b0
3’h1
4’h2
8’h0
4’h0
AIF WL = 16 bit
0.0005
0.2665
14
8’h45
1’b0
3’h4
4’h2
8’h1D
4’h0
Set HPL_ENA_OUTP
& HPR_ENA_OUTP
0.0005
0.2670
15
8’h45
1’b0
3’h4
4’h3
8’h1F
4’h0
Set HPL_RMV_SHRT
& HPR_RMV_SHRT
0.0005
0.2675
16
8’hFE
1’b0
3’h0
4’h0
8’h0
4’h0
Dummy Write for
expansion
0.0005
0.2680
17
8’h5
1’b1
3’h0
4’h3
8’h0
4’h8
DAC Soft unmute, wait
16.5ms
0.0165
0.2845
18
8’h20
1’b0
3’h1
4’h4
8’h03
4’h0
LMICBOOST = 11
0.0005
0.0005
19
8’h21
1’b0
3’h1
4’h4
8’h03
4’h0
RMICBOOST = 11
0.0005
0.0010
20
8’h19
1’b0
3’h4
4’h1
8’h19
4’h0
AINL = 1, AINR = 1,
MICB = 1
0.0005
0.0015
21
8’h3C
1’b0
3’h5
4’h2
8’h33
4’hC
Enable Servo on
inputs, trigger startup,
wait 256ms
0.2560
0.2575
22
8’hFE
1’b0
3’h0
4’h0
8’h00
4’h0
Dummy Write for
expansion
0.0005
0.2580
23
8’h19
1’b0
3’h1
4’h2
8’h3
4’h0
ADCL = 1, ADCR = 1
0.0005
0.2585
24
8’h20
1’b0
3’h1
4’h4
8’h0
4’h0
LMICBOOST = 00
0.0005
0.2590
25
8’h21
1’b0
3’h1
4’h4
8’h0
4’h0
RMICBOOST = 00
0.0005
0.2595
26
8’hFE
1’b1
3’h0
4’h0
8’h00
4’h0
Dummy Write for
expansion
0.0005
0.2600
27
8’h5
1’b0
3’h0
4’h3
8’h1
4’h8
DAC Soft mute, wait
16.5ms
0.0165
0.0165
28
8’h00
1’b0
3’h0
4’h7
8’h01
4’h0
LINMUTE = 1
0.0005
0.0170
29
8’h01
1’b0
3’h1
4’h7
8’h03
4’h0
RINMUTE = 1, IPVU
0.0005
0.0175



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