MCP47DA1 datasheet(68/76 Pages) MICROCHIP

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MCP47DA1

DS25118D-page 68

 2012-2013 Microchip Technology Inc.

APPENDIX B: TERMINOLOGY

B.1

Resolution

The resolution is the number of DAC output states that

divide the full-scale range. For the 6-bit DAC, the

resolution is 26, meaning the DAC code ranges from 0

to 64.

B.2

Least Significant Bit (LSb)

Normally, this is thought of as the ideal voltage

difference between two successive codes. This bit has

the smallest value or weight of all bits in the register.

For a given output voltage range, which is typically the

voltage between the full-scale voltage and the zero-

scale voltage (VOUT(FS) - VOUT(ZS)), it is divided by the

resolution of the device (Equation B-1).

EQUATION B-1:

LSb VOLTAGE

CALCULATION

B.3

Monotonic Operation

Monotonic operation means that the device’s output

voltage (VOUT) increases with every one code step

(LSb) change (from terminal B to terminal A). The VOUT

voltage (VW voltage) is the sum of all the Step voltages

plus the voltage at zero scale (VZS). The zero-scale

voltage is dependent on the resistance between the tap

0 point and the B Terminal.

FIGURE B-1:

VW (VOUT).

B.4

Full-Scale Error (FSE)

The Full-Scale Error (FSE) is the difference between

the ideal and measured DAC output voltage with the

wiper’s position is set to its maximum (wiper code =

40h); see Figure B-3. Full-scale error may also be

thought of as the sum of the offset error plus gain error.

See Figure 2-23 through Figure 2-33 for FSE

characterization graphs.

EQUATION B-2:

FULL-SCALE ERROR

B.5

Zero-Scale Error (ZSE)

The Zero-Scale Error (ZSE) is the difference between

the ideal and measured VOUT voltage with the wiper

position set to its minimum (wiper code = 00h); see

Figure B-3. The zero-scale error is the same as the off-

set error for this case (wiper code = 00h).

See Figure 2-34 through Figure 2-44 for ZSE

characterization graphs.

EQUATION B-3:

ZERO-SCALE ERROR

B.6

Total Unadjusted Error

The total unadjusted error is the difference between the

ideal and measured VOUT voltage. Typically, calibration

of the output voltage is implemented to improve system

performance.

See Figure 2-45 through Figure 2-55 and Figure 2-75

through Figure 2-78 for total unadjusted error

characterization graphs.

VLSb =

VOUT(FS) - VOUT(ZS)

2N = 64 (MCP47DA1)

0x40

0x3F

0x3E

0x03

0x02

0x01

0x00

Voltage (VW ~= VOUT)

(@ tap)

VS0

VS1

VS3

VS63

VS64

VW =

VSn + VZS(@ Tap 0)

n = 0

n = ?

FSE =

VOUT(@FS) - VIDEAL(@FS)

VLSb

Where:

FSE is expressed in LSb

VOUT(@FS) is the VOUT voltage when the DAC

VIDEAL(@FS) is the ideal output voltage when the

DAC register code is at Full Scale.

VLSb is the delta voltage of one DAC register code

step (such as code 20h to code 21h).

ZSE =

VOUT(@ZS)

VLSb

Where:

FSE is expressed in LSb

VOUT(@ZS) is the VOUT voltage when the DAC

VLSb is the delta voltage of one DAC register code

step (such as code 20h to code 21h).

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