IMX53IEC datasheet(3/173 Pages) FREESCALE

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Introduction

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

1.2

Features

The i.MX53 multimedia applications processor (AP) is based on the ARM Platform, which has the

following features:

•

MMU, L1 instruction and L1 data cache

•

Unified L2 cache

•

Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz

•

Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)

coprocessor supporting VFPv3

•

TrustZone

The memory system consists of the following components:

•

Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

•

Level 2 cache:

— Unified instruction and data (256 Kbyte)

•

Level 2 (internal) memory:

— Boot ROM, including HAB (64 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

— Secure/non-secure RAM (16 Kbyte)

•

External memory interfaces:

— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte

— 32-bit LPDDR2

— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC

— 8/16-bit NOR Flash, PSRAM, and cellular RAM.

— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.

— 8-bit Asynchronous (DTACK mode) EIM interface.

— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects

EIM port, as primary muxing at system boot.

— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O

mode)

The i.MX53 system is built around the following system on chip interfaces:

•

64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,

GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.

•

32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.

•

32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral

devices operating at 66 MHz.

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