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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IMX53IEC 데이터시트(PDF) 63 Page - Freescale Semiconductor, Inc |
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IMX53IEC 데이터시트(HTML) 63 Page - Freescale Semiconductor, Inc |
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63 / 173 page  Electrical Characteristics i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 63 Figure 29 and Table 41 show the address and control timing parameters for LPDDR2. Figure 29. DDR SDRAM Address and Control Timing Parameters for LPDDR2 Figure 30 and Table 42 show the data write timing parameters. Figure 30. DDR SDRAM Data Write Cycle Table 41. DDR SDRAM Timing Parameter Table for LPDDR21 2 1 All timings are refer to Vref level cross point. 2 Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF. ID Parameter Symbol SDCLK = 400 MHz Units Min Max LP1 SDRAM clock high-level width tCH 0.45 0.55 tCK LP2 SDRAM clock low-level width tCL 0.45 0.55 tCK LP3 CS, CKE setup time tIS 0.3 — ns LP4 CS, CKE hold time tIH 0.3 — ns LP3 CA setup time tIS 0.3 — ns LP4 CA hold time tIH 0.3 — ns CK CS CKE CA LP4 LP4 LP3 LP4 LP3 LP2 LP3 LP3 LP1 SDCLK SDCLK_B DQS (output) DQ (output) DQM (output) Data Data Data Data Data Data Data Data DM DM DM DM DM DM DM DM DDR17 DDR17 DDR17 DDR17 DDR18 DDR18 DDR18 DDR18 DDR21 DDR23 DDR22 |
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