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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IMX53IEC 데이터시트(PDF) 68 Page - Freescale Semiconductor, Inc |
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IMX53IEC 데이터시트(HTML) 68 Page - Freescale Semiconductor, Inc |
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68 / 173 page  i.MX53 Applications Processors for Industrial Products, Rev. 6 68 Freescale Semiconductor Electrical Characteristics 4.7.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 48 shows the interface timing values. The number field in the table refers to timing signals found in Figure 34 and Figure 35. Table 48. Enhanced Serial Audio Interface (ESAI) Timing No. Characteristics1’2,3 Symbol Expression3 Min Max Condition4 Unit 62 Clock cycle5 tSSICC 4 × Tc 4 × Tc 30.0 30.0 — — i ck i ck ns 63 Clock high period • For internal clock —2 × Tc − 9.0 6 — — ns • For external clock — 2 × Tc 15 — — 64 Clock low period • For internal clock —2 × Tc − 9.0 6 — — ns • For external clock — 2 × Tc 15 — — 65 SCKR rising edge to FSR out (bl) high — — — — — — 17.0 7.0 x ck i ck a ns 66 SCKR rising edge to FSR out (bl) low — — — — — — 17.0 7.0 x ck i ck a ns 67 SCKR rising edge to FSR out (wr) high6 — — — — — — 19.0 9.0 x ck i ck a ns 68 SCKR rising edge to FSR out (wr) low6 — — — — — — 19.0 9.0 x ck i ck a ns 69 SCKR rising edge to FSR out (wl) high — — — — — — 16.0 6.0 x ck i ck a ns 70 SCKR rising edge to FSR out (wl) low — — — — — — 17.0 7.0 x ck i ck a ns 71 Data in setup time before SCKR (SCK in synchronous mode) falling edge — — — — 12.0 19.0 — — x ck i ck ns 72 Data in hold time after SCKR falling edge — — — — 3.5 9.0 — — x ck i ck ns 73 FSR input (bl, wr) high before SCKR falling edge6 — — — — 2.0 12.0 — — x ck i ck a ns 74 FSR input (wl) high before SCKR falling edge — — — — 2.0 12.0 — — x ck i ck a ns 75 FSR input hold time after SCKR falling edge — — — — 2.5 8.5 — — x ck i ck a ns 78 SCKT rising edge to FST out (bl) high — — — — — — 18.0 8.0 x ck i ck ns 79 SCKT rising edge to FST out (bl) low — — — — — — 20.0 10.0 x ck i ck ns |
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