IMX53IEC datasheet(60/173 Pages) FREESCALE

60 / 173 page

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select

Ref No.

Parameter

Determination by

Synchronous measured

parameters 12

Min

Max

(If 133 MHz is

supported by SOC)

Unit

WE31

CSx_B valid to Address Valid

WE4 - WE6 - CSA3

—

3 - CSA

WE32

Address Invalid to CSx_B

invalid

WE7 - WE5 - CSN4

—3 - CSN

WE32A(

muxed

A/D

CSx_B valid to Address Invalid

t5 + WE4 - WE7 + (ADVN +

ADVA + 1 - CSA3)

-3 + (ADVN +

ADVA + 1 - CSA)

—ns

WE33

CSx_B Valid to WE_B Valid

WE8 - WE6 + (WEA - CSA)

—

3 + (WEA - CSA)

WE34

WE_B Invalid to CSx_B Invalid

WE7 - WE9 + (WEN - CSN)

—

3 - (WEN_CSN)

WE35

CSx_B Valid to OE_B Valid

WE10 - WE6 + (OEA - CSA)

—

3 + (OEA - CSA)

WE35A

(muxed

A/D)

CSx_B Valid to OE_B Valid

WE10 - WE6 + (OEA + RADVN

+ RADVA + ADH + 1 - CSA)

-3 + (OEA +

RADVN+RADVA+

ADH+1-CSA)

3 + (OEA +

RADVN+RADVA+AD

H+1-CSA)

WE36

OE_B Invalid to CSx_B Invalid

WE7 - WE11 + (OEN - CSN)

—

3 - (OEN - CSN)

WE37

CSx_B Valid to BEy_B Valid

(Read access)

WE12 - WE6 + (RBEA - CSA)

—

3 + (RBEA6 - CSA)

WE38

BEy_B Invalid to CSx_B Invalid

(Read access)

WE7 - WE13 + (RBEN - CSN)

—

3 - (RBEN7- CSN)

WE39

CSx_B Valid to ADV_B Valid

WE14 - WE6 + (ADVA - CSA)

—

3 + (ADVA - CSA)

WE40

ADV_B Invalid to CSx_B

Invalid (ADVL is asserted)

WE7 - WE15 - CSN

—

3 - CSN

WE40A

(muxed

A/D)

CSx_B Valid to ADV_B Invalid

WE14 - WE6 + (ADVN + ADVA

+ 1 - CSA)

-3 + (ADVN +

ADVA + 1 - CSA)

3 + (ADVN + ADVA +

1 - CSA)

WE41

CSx_B Valid to Output Data

Valid

WE16 - WE6 - WCSA

—

3 - WCSA

WE41A

(muxed

A/D)

CSx_B Valid to Output Data

Valid

WE16 - WE6 + (WADVN +

WADVA + ADH + 1 - WCSA)

—

3 + (WADVN +

WADVA + ADH + 1 -

WCSA)

WE42

Output Data Invalid to CSx_B

Invalid

WE17 - WE7 - CSN

—

3 - CSN

MAXCO Output max. delay from internal

driving ADDR/control FFs to

chip outputs.

—

MAXCS

Output max. delay from CSx

internal driving FFs to CSx out.

—

MAXDI

DATA MAXIMUM delay from

chip input data to its internal FF

5—

—

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