AD9523-1SLASHPCBZ datasheet(4/60 Pages) AD

4 / 60 page

AD9523-1

Rev. B | Page 4 of 60

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HSTL Mode, 16 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

24.2

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

59.1

f = 983.04 MHz

HSTL Mode, 8 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

16.7

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

42.5

f = 983.04 MHz

CMOS Mode (Single-Ended)

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

2.4

f = 15.36 MHz, 10 pF Load

CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON

Channel x control register, Bit 4 = 1

LVDS Mode, 7 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

10.8

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

29.8

f = 983.04 MHz

LVDS Mode, 3.5 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

6.5

7.5

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

26.3

f = 983.04 MHz

LVPECL Mode

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

12.4

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

31.2

f = 983.04 MHz

HSTL Mode, 16 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

24.3

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

59.1

f = 983.04 MHz

HSTL Mode, 8 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

12.7

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

31.8

f = 983.04 MHz

1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 68 and Pin 67,

respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 65 and Pin 64, respectively).

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