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AD9523-1/PCBZ 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD9523-1/PCBZ
상세설명  Low Jitter Clock Generator
PDF  60 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9523-1/PCBZ 데이터시트(HTML) 6 Page - Analog Devices

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AD9523-1
Rev. B | Page 6 of 60
REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIFFERENTIAL MODE
Input Frequency Range
400
MHz
Input Slew Rate (OSC_IN)
400
V/μs
Minimum limit imposed for jitter
performance
Common-Mode Internally
Generated Input Voltage
0.6
0.7
0.8
V
Input Common-Mode Range
1.025
1.475
V
For dc-coupled LVDS (maximum swing)
Differential Input Voltage,
Sensitivity Frequency < 250 MHz
100
mV p-p
Capacitive coupling required; can
accommodate single-ended input
by ac grounding of unused input;
instantaneous voltage on either pin
must not exceed the 1.8 V dc supply rails
Differential Input Voltage,
Sensitivity Frequency > 250 MHz
200
mV p-p
Capacitive coupling required; can
accommodate single-ended input
by ac grounding of unused input;
instantaneous voltage on either pin
must not exceed the 1.8 V dc supply rails
Differential Input Resistance
4.8
kΩ
Differential Input Capacitance
1
pF
Duty Cycle
Duty cycle limits are set by pulse width
high and pulse width low
Pulse Width Low
1
ns
Pulse Width High
1
ns
CMOS MODE, SINGLE-ENDED INPUT
Input Frequency Range
250
MHz
Input High Voltage
2.0
V
Input Low Voltage
0.8
V
Input Capacitance
1
pF
Duty Cycle
Duty cycle limits are set by pulse width
high and pulse width low
Pulse Width Low
1.6
ns
Pulse Width High
1.6
ns
OSC_CTRL OUTPUT CHARACTERISTICS
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT VOLTAGE
High
VDD3_PLL − 0.15
V
RLOAD > 20 kΩ
Low
150
mV
REF_TEST INPUT CHARACTERISTICS
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REF_TEST INPUT
Input Frequency Range
250
MHz
Input High Voltage
2.0
V
Input Low Voltage
0.8
V



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