AD9523-1SLASHPCBZ datasheet(5/60 Pages) AD

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AD9523-1

Rev. B | Page 5 of 60

POWER DISSIPATION

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION

Does not include power dissipated in termination resistors

Typical Configuration

898

984.7

Clock distribution outputs running as follows: 7 LVPECL at 122.88 MHz,

3 LVDS (3.5 mA) at 61.44 MHz, 3 LVDS (3.5 mA) at 245.76 MHz, 1 single-

ended CMOS 10 pF load at 122.88 MHz, 1 differential input reference

at 30.72 MHz; fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1

at 3, and VCO Divider M2 is off; PLL2 BW = 530 kHz

PD, Power-Down

98.2

PD pin pulled low, with typical configuration conditions

INCREMENTAL POWER DISSIPATION

Base Typical Configuration

393

434.7

Absolute total power with clock distribution; 1 LVPECL output (OUT0)

running at 122.88 MHz; 1 differential input reference at 30.72 MHz;

fVCXO = 122.88 MHz, fVCO = 2949.12 MHz, VCO Divider M1 at 3; VCO

Divider M2 is off

Switched to One Input,

Reference Single-Ended Mode

−28.5

−8

Running at 30.72 MHz

Switched to Two Inputs,

Reference Differential Mode

44.6

Running at 30.72 MHz

Switched to Two Inputs,

Reference Single-Ended Mode

−27.5

−5.1

Running at 30.72 MHz

VCO Divider M2

88.3

Incremental power increase VCO Divider M2 (OUT4) from base typical

Output Distribution, Driver On

Incremental power increase (OUT1) from base typical

LVDS Mode

3.5 mA

34.8

Single 3.5 mA LVDS output at 122.88 MHz

105.6

Single 3.5 mA LVDS output at 983.04 MHz

7 mA

Single 7 mA LVDS output at 122.88 MHz

141

164

Single 7 mA LVDS output at 983.04 MHz

LVPECL Mode

Single LVPECL output at 122.88 MHz

144

159

Single LVPECL output at 983.04 MHz

HSTL Mode

8 mA

Single 8 mA HSTL output at 122.88 MHz

143

165

Single 8 mA HSTL output at 983.04 MHz

16 mA

Single 16 mA HSTL output at 122.88 MHz

153

176

Single 16 mA HSTL output at 983.04 MHz

CMOS Mode

6.6

7.9

Single 3.3 V CMOS output at 15.36 MHz

9.9

11.9

Dual complementary 3.3 V CMOS output at 15.36 MHz

9.9

11.9

Dual in-phase 3.3 V CMOS output at 15.36 MHz

Output Distribution, Driver On

Lower power mode on, (Channel x control register, Bit 4 = 1)

LVDS Mode

3.5 mA

28.5

33.6

Single 3.5 mA LVDS output at 122.88 MHz

105.6

Single 3.5 mA LVDS output at 983.04 MHz

7 mA

42.9

Single 7 mA LVDS output at 122.88 MHz

113.7

Single 7 mA LVDS output at 983.04 MHz

LVPECL Mode

40.5

Single LVPECL output at 122.88 MHz

100

110

Single LVPECL output at 983.04 MHz

HSTL Mode

8 mA

39.1

Single 8 mA HSTL output at 122.88 MHz

108.1

Single 8 mA HSTL output at 983.04 MHz

16 mA

55.2

Single 16 mA HSTL output at 122.88 MHz

153

176

Single 16 mA HSTL output at 983.04 MHz

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