AD9523-1SLASHPCBZ datasheet(8/60 Pages) AD

8 / 60 page

AD9523-1

Rev. B | Page 8 of 60

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CMOS MODE

Maximum Output Frequency

250

MHz

Rise Time/Fall Time (20% to 80%)

387

665

15 pF load

Duty Cycle

f = 250 MHz

Output Voltage High

Output driver static

VDD − 0.25

Load current = 10 mA

VDD − 0.1

Load current = 1 mA

Output Voltage Low

Output driver static

0.2

Load current = 10 mA

0.1

Load current = 1 mA

TIMING ALIGNMENT CHARACTERISTICS

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT TIMING SKEW

Delay off on all outputs; maximum

deviation between rising edges of outputs;

all outputs are on, unless otherwise noted

Between Outputs in Same Group1

LVPECL, HSTL, and LVDS

Between LVPECL, HSTL, and

LVDS Outputs

183

CMOS

Between CMOS Outputs

100

300

Single-ended, true phase, high-Z mode

Mean Delta Between Groups1

Adjustable Delay

Steps

Resolution step; for example, 8 × 0.5/1 GHz

Resolution Step

500

½ period of 1 GHz

Zero Delay

Between Input Clock Edge on

REFA or REFB to ZD_IN Input

Clock Edge, External Zero

Delay Mode

150

500

PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 μA,

RZERO = 10 kΩ, antibacklash pulse width is

at maximum, BW = 40 Hz, REFA and

ZD_IN are set to differential mode

1 There are three groups of outputs. They are as follows: the top outputs group, consisting of OUT0, OUT1, OUT2, and OUT3; the right outputs group, consisting of

OUT4, OUT5, OUT6, OUT7, OUT8, and OUT9; and the bottom outputs group, consisting of OUT10, OUT11, OUT12, and OUT13.

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