AD9523-1SLASHPCBZ datasheet(10/60 Pages) AD

10 / 60 page

AD9523-1

Rev. B | Page 10 of 60

STATUS OUTPUT PINS—STATUS1, STATUS0

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE

Output High

2.94

Output Low

0.4

SERIAL CONTROL PORT—SPI MODE

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 40 kΩ pull-up resistor

Voltage

Input Logic 1

2.0

Input Logic 0

0.8

Current

Input Logic 1

μA

Input Logic 0

−110

μA

The minus sign indicates that, due to the

internal pull-up resistor, current is flowing out

of the AD9523-1

Input Capacitance

SCLK (INPUT) IN SPI MODE

SCLK has an internal 40 kΩ pull-down resistor

in SPI mode but not in I2C mode

Voltage

Input Logic 1

2.0

Input Logic 0

0.8

Current

Input Logic 1

240

μA

Input Logic 0

μA

Input Capacitance

SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)

Voltage

Input Logic 1

2.0

Input Logic 0

0.8

Current

Input Logic 1

μA

Input Logic 0

μA

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

3.3

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup, tS

CS to SCLK Setup and Hold, tS, tC

CS Minimum Pulse Width High, tPWH

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