STM8S103F2 datasheet(61/117 Pages) STMICROELECTRONICS

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Unit

Max

(1)

Typ

Conditions

Parameter

Symbol

(6)

HSI

(after

Flash in operating

mode

(5)

MVR voltage

regulator

off

(4)

Wakeup time active

halt mode to run

mode

(3)

wakeup)

(6)

HSI

(after

Flash in

power-down

MVR voltage

regulator

Wakeup time active

halt mode to run

wakeup)

mode

(5)

off

(4)

mode

(3)

Flash in operating mode

(5)

Wakeup time from

halt mode to run

tWU(H)

Flash in power-down mode

(5)

mode

(3)

(1) Data guaranteed by design, not tested in production.

(2) t

WU(WFI) = 2 x 1/fmaster + 6 x 1/fCPU.

(3) Measured from interrupt event to interrupt vector fetch.

(4) Configured by the REGAH bit in the CLK_ICKR register.

(5) Configured by the AHALT bit in the FLASH_CR1 register.

(6) Plus 1 LSI clock depending on synchronization.

Total current consumption and timing in forced reset state

10.3.2.6

Table 30: Total current consumption and timing in forced reset state

Unit

Max

(1)

Typ

Conditions

Parameter

Symbol

μA

400

VDD = 5 V

Supply current in reset

state

(2)

IDD(R)

300

VDD = 3.3 V

μs

150

Reset pin release to

vector fetch

tRESETBL

(1) Data guaranteed by design, not tested in production.

(2) Characterized with all I/Os tied to V

SS.

Current consumption of on-chip peripherals

10.3.2.7

Subject to general operating conditions for VDD and TA.

61/117

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Electrical characteristics

STM8S103K3 STM8S103F3 STM8S103F2

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