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STM8S103F2 데이터시트(PDF) 81 Page - STMicroelectronics

부품명 STM8S103F2
상세설명  Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
PDF  117 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM8S103F2 데이터시트(HTML) 81 Page - STMicroelectronics

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Figure 36: Typical NRST pull-up resistance vs VDD @ 4 temperatures
Figure 37: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table
38: I/O static characteristics ), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 100 nF.
81/117
DocID15441 Rev 9
Electrical characteristics
STM8S103K3 STM8S103F3 STM8S103F2



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