STM8S103F2 datasheet(23/117 Pages) STMICROELECTRONICS

23 / 117 page

Alternate

function after

remap [option

bit]

Default alternate

function

Main

function

(after

reset)

Output

Input

Type

name

LQFP/

UFQFP

SDIP

Speed

High

sink

(1)

Ext.

interrupt

wpu

floating

SPI master in/ slave

out

Port C7

I/O

PC7/

SPI_MISO

Configurable

clock output

[AFR5]

Timer 1 - break input

Port D0

I/O

PD0/

TIM1_BKIN

[CLK_CCO]

SWIM data interface

Port D1

I/O

PD1/

SWIM

(4)

Timer 2 -

channel

3[AFR1]

Port D2

I/O

PD2

[TIM2_CH3]

Timer 2 - channel

2/ADC external

trigger

Port D3

I/O

PD3/

TIM2_CH2/

ADC_ETR

Timer 2 - channel

1/BEEP output

Port D4

I/O

PD4/BEEP/

TIM2_CH1

UART1 data transmit

Port D5

I/O

PD5/

UART1_TX

UART1 data receive

Port D6

I/O

PD6/

UART1_RX

Timer 1 -

channel 4

[AFR6]

Top level interrupt

Port D7

I/O

PD7/ TLI

[TIM1_CH4]

(1)

I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total

driven current must respect the absolute maximum ratings (see Electrical characteristics).

(2)

When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking

up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode if Halt/Active-halt

is used in the application.

(3)

In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not

implemented).

(4)

The PD1 pin is in input pull-up during the reset phase and after internal reset release.

23/117

DocID15441 Rev 9

Pinout and pin description

STM8S103K3 STM8S103F3 STM8S103F2

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