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AN1105 데이터시트(PDF) 12 Page - STMicroelectronics |
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AN1105 데이터시트(HTML) 12 Page - STMicroelectronics |
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12 / 100 page ![]() 12/100 ST7 pCAN PERIPHERAL DRIVER Figure 8. CAN Error States When both counters contain values between 0 and 127, the CAN node is in Error Active state, which means that it can send and receive normally. If it detects an error, it will send Ac- tive Error flags. When one of the two counters reaches a value between 128 and 255, the node is in Error Passive state. It will go on receiving and sending normally but will only be authorized to send Passive Error flags. Therefore, if this node causes trouble by sending unjustified Error frames, it will not disturb the network for too long. When one of the counters reaches a value over 255 (i.e. it overflows), the CAN node enters Bus Off state. It is then physically disconnected from the bus. It can go back to Active mode if it successfully detects 128x11 consecutive recessive bits on the bus. 1.6 ST7 PCAN PERIPHERAL 1.6.1 Main Features The ST7 pCAN peripheral implements a CAN 2.0B passive protocol. This means that ex- tended frames are recognized and acknowledged, but cannot be saved nor processed by the microcontroller. – The pCAN peripheral is based on three 10-byte hardware buffers that can be used either for transmission or reception. They are prioritized in the increasing priority order 1 to 3 for transmission and 3 to 1 for reception. Each buffer has a control register indicating if a job is pending, if new data has been received or if the buffer is currently being written/read. A bit in this register is used to lock the buffer for transmission (See ST72511 datasheet p.116). – The baud rate is programmable up to 1 Mbps. The length of the bit synchronisation fields is also programmable. The baud rate is configured by setting three values: the size of time quanta (in clock ticks) and the length of the two synchronization segments (in time quanta). See ST72511 datasheet p.114, Baud Rate Prescaler Register and Bit Timing Register. Error Active Error Passive Bus Off TEC >255 128 blocks of 11 suc- cessive recessive bits TEC>127 or REC>127 TEC<127 and REC<127 |
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