STC5425 datasheet(25/48 Pages) CONNOR-WINFIELD

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Page 25 of 48

TM113

Rev:P1.3

Date: September 20, 2011

STC5425

Line Card Clock

Data sheet

Preliminary

General Register Operation

The STC5425 device has 1, 2, 3, and 4 byte registers. One-byte registers are read and written directly. Multiple

-byte registers must be read and written in a specific manner and order, as follows:

Multibyte register reads

A multi byte register read must commence with a read of the least significant byte first. This triggers a transfer

of the remaining byte(s) to a holding register, ensuring that the remaining data will not change with the continu-

ing operation of the device. The remaining byte(s) must be read consecutively with no intervening read/writes

from/to other registers.

Multibyte register writes

A multi byte register write must commence with a write to the least significant byte first. Subsequent writes to

the remaining byte(s) must be performed in ascending byte order, consecutively, with no intervening read/

writes from/to other registers, but with no timing restrictions. Multibyte register writes are temporarily stored in

a holding register, and are transferred to the target register when the most significant byte is written.

Chip_ID, 0x00 (R)

Indicates chip’s ID number

Chip_Rev, 0x02 (R)

Indicates the revision number of STC5425

Chip_Sub_Rev, 0x03 (R)

Indicates the firmware revision number of STC5425

Fill_Obs_Window, 0x07 (R/W)

Sets the fill observation window size for the reference activity monitor to (m+1) ms. The window size can be set

from 1ms to 16ms.

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x00

0x25

0x01

0x54

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x02

Revision Number

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x03

Sub-Revision Number

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x07

Not used

Leaky bucket fill observation window, m = 0 ~ 15

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