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STC5425 데이터시트(PDF) 38 Page - Connor-Winfield Corporation

부품명 STC5425
상세설명  Line Card Clock
PDF  48 Pages
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제조업체  CONNOR-WINFIELD [Connor-Winfield Corporation]
홈페이지  http://www.conwin.com
Logo CONNOR-WINFIELD - Connor-Winfield Corporation

STC5425 데이터시트(HTML) 38 Page - Connor-Winfield Corporation

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TM113
Rev:P1.3
Date: September 20, 2011
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC5425
Line Card Clock
Data sheet
Preliminary
Phase skew adjust for synthesizers based on which synthesizer index is selected at the register
Synth_Index_Select. See description of the register Synth_Index_Select. The adjustment is from -6400/128
ns to 6396.875/128 ns, which is -50ns ~ 49.976 ns, in 3.125/128 ns steps, 2’s complement.
Default value: 0 (For all the synthesizers)
CLK1_Signal_Level 0x50 (R/W)
Selects the signal level for clock outputs CLK1
0 = LVPECL, 1 = LVDS
Default value: 0
CLK1_Sel, 0x51(R/W)
Selects clock output CLK1 derived from synthesizer G1 or put in tri-state.
Default value: 0
CLK2_Sel, 0x52 (R/W)
Selects the clock output CLK2 derived from synthesizer G4. Signal level of CLK2 is LVCMOS.
Default value: 0
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x50
Not used
CLK1 Signal Level
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x51
Not used
CLK1 Synthesizer Select
Bits 1 ~ 0
CLK1 Synthesizer Select
0, 2, 3
Put CLK1 in tri-state mode
1
Synthesizer G1
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x52
Not used
CLK2 Synthesizer Select
Bits 1 ~ 0
CLK3 Synthesizer Select
0, 2, 3
Put CLK2 in tri-state mode
1
Synthesizer G4



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