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TM113

Rev:P1.3

Date: September 20, 2011

© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice

STC5425

Line Card Clock

Data sheet

Preliminary

Table of Figures

Figure 1: Functional Block Diagram................................................................................................................... 1

Figure 2: Activity Monitor ................................................................................................................................. 19

Figure 3: Reference Qualification Scheme ...................................................................................................... 19

Figure 4: Automatic Reference Elector States................................................................................................. 20

Figure 5: Output Clocks CLK1 ......................................................................................................................... 21

Figure 6: Output Clocks CLK2 ......................................................................................................................... 21

Figure 7: Output Clocks CLK8K and CLK2K ................................................................................................... 21

Figure 8: SPI Bus, Read access (Pin CLKE = Low) ........................................................................................ 23

Figure 9: SPI Bus Timing, Read access (Pin CLKE = High) .......................................................................... 23

Figure 10: SPI Bus Timing, Write access ........................................................................................................ 24

Figure 11: Noise Transfer Functions .............................................................................................................. 43

Figure 12: Power and Ground ........................................................................................................................ 45