Z8018233FSC datasheet(76/109 Pages) ZILOG

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3-76

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

PARALLEL PORTS REGISTERS

The Z80182/Z8L182 has three 8-bit bi-directional Ports.

Each bit is individually programmable for input or output.

The Ports consist of two registers the Port Direction Control

only the lowest eight address lines are decoded. Bits PC7

and PC6 are input only bits and have the special function

of reading the external value of the /INT2 and /INT1 pins.

Writing ‘1’ to these bits will clear the edge detect interrupt

logic when operating /INT2 and/or /INT1 in edge detect

mode.

When Port B and Port C bits 5-0 are deselected in the

System Configuration Register, the Data and Data Direction

Registers are still available as read/write scratch registers.

If a Port is deselected and if the DDR bit is a ‘0’, then the

written value to that bit will be latched and this value can be

read back. If a Port is deselected and if the DDR bit is a ‘1’,

then you could read only the external pin value; any write

to that bit is latched but can be read back only with DDR=0.

11111

PB Data Direction Register

0=Output

1=Input

11111

PA Data Direction Register

0=Output

1=Input

Figure 83. PA, Port A, Data Direction Register

(Z180 MPU Read/Write, Address xxEDH)

The data direction register determines which are inputs

and outputs in the PA Data Register. When a bit is set to 1

the corresponding bit in the PA Data Register is an input.

If the bit is 0, then the corresponding bit is an output.

XXXX

XXX

PA Data Register

Figure 84. PA, Port A, Data Register

(Z180 MPU Read/Write, Address xxEEH)

When the Z180 MPU writes to the PA Data Register the

data is stored in the internal buffer. The values of the PA

Data Register are undefined after reset. Any bits that are

output are then sent on to the output buffers.

When the Z180 MPU reads the PA Data Register the data

on the external pins is returned.

Figure 85. PB, Port B, Data Direction Register

(Z180 MPU Read/Write, Address xxE4H)

The data direction register determines which are inputs

and outputs in the PB Data Register. When a bit is set to 1

the corresponding bit in the PB Data Register is an input.

If the bit is 0 then the corresponding bit is an output.

Figure 86. PB, Port B, Data Register

(Z180 MPU, Address xxE5H)

When the Z180 MPU writes to the PB Data Register the

data is stored in the internal buffer. The values of Port B

data register are undefined after reset. Any bits that are

output are then sent on to the output buffers.

When the Z180 MPU reads the PB Data Register, the data

on the external pins is returned.

XXX

PB Data Register

11111

PC Direction Register

Figure 87. PC, Port C, Data Direction Register

(Z180 MPU Read/Write, Address xxDDH)

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