Z8018233FSC datasheet(58/109 Pages) ZILOG

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3-58

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS

Table 12b. Data Bus Direction (Z182 Bus Master)

Interrupt Acknowledge Transaction

Intack For

On-Chip

Off-Chip

Peripheral (IEI=1)

Peripheral (IEI=0)

Z80182/Z8L182

Data Bus

(DD

OUT=0)

Z80182/Z8L182

Data Bus

Out

(DD

OUT=1)

Table 13a. Data Bus Direction (Z80182/Z8L182

is not Bus Master)

I/O And Memory Transactions

I/O Write

I/O Read

I/O Write

I/O Read

Write

Read

to On-Chip

From On-Chip

to Off-Chip

From Off-Chip

From

Z80182

Peripherals

Memory

Mode

Refresh

Idle Mode

Z80182

Out

/Z8L182

Data Bus

OUT=0)

Z80182

Out

/Z8L182

Data Bus

(DD

OUT=1)

Table 13b. Data Bus Direction (Z80182/Z8L182

is not Bus Master)

Interrupt Acknowledge Transaction

Intack For

On-Chip

Off-Chip

Peripheral

Z80182/Z8L182

Data Bus

Out

(DD

OUT=0)

Z80182/Z8L182

Data Bus

Out

(DD

OUT=1)

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