Z8018233FSC datasheet(64/109 Pages) ZILOG

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DS971820600

Figure 61. IUS/IP Register

(Z180 MPU, Address xxFEH)

Bit 7 Interrupt Under Service (Read/Write)

This bit represents a logical OR of each individual IUS bit

for the internal MIMIC interrupt daisy chain. An IUS bit is set

when an interrupt is registered (IP set) and enabled (IE

set), the incoming IEI daisy chain is active (chain enabled)

and an interrupt acknowledge cycle is entered. By writing

a 1 to this bit the highest priority IUS bit that is set will be

reset. Writing a 0 to this bit has no effect.

This should be done at the end of every MIMIC Interrupt

Service routine.

Bit 6 Transmit Holding Register Written (Read Only)

This bit is set when the PC/XT/AT writes to the Transmit

Holding Register. It is reset when the Z180 MPU reads the

Transmit Holding Register. In FIFO mode, this bit is set

when the trigger level is reached (4,8,14 bytes available).

Note: The THR bit is set (interrupts) when the transmitter

FIFO reaches the data available trigger level set in the MPU

FCR control register. The bit and interrupt source is cleared

when the number of data bytes falls below the set trigger

level.

00000

Interrupt Under Service (RD)

Reset Highest IUS (WR)

Interrupt Pending

6 THR Write

5 TTO Transmitter Timeout

4 RBR Read

3 MCR Write

2 LCR Write

1 DLL Write

1 DLM Write

0 FCR Write or Tx Overrun

IUS/IP Register

The IUS/IP Register is used by the Z180™ MPU to determine

the source of the interrupt. This register will have the

appropriate bit set when an interrupt occurs.

Bit 5 Transmitter Timeout with Data in FIFO (Read

Only)

This bit is set when the transmitter FIFO has been idle (no

read or write and timer decrements to zero) with data bytes

below the trigger level. It is cleared when the FIFO is read

or written.

Bit 4 Receive Buffer Read (Read Only)

This bit is set when the PC/XT/AT reads the Receive Buffer

Receive Buffer Register. In FIFO mode, this bit is set upon

the PC reading all the data in the receive FIFO. Note: RBR

is set and interrupts when the receive FIFO has been

emptied by the PC. This bit and interrupt are cleared when

one or more bytes are written into the receive FIFO by the

MPU.

Bit 3 Modem Control Register Write (Read Only)

This bit is set when the PC/XT/AT writes to the Modem

Control Register. It is reset when the Z180™ MPU reads the

Modem Control Register.

Bit 2 Line Control Register Write (Read Only)

This bit is set when the PC/XT/AT writes to the Line Control

Control Register.

Bit 1 Divisor Latch LS/MS Write (Read Only)

This bit is set when the PC/XT/AT writes to the Divisor Latch

Least Significant or Most Significant bytes. It is reset when

the PC reads the LS/MS register(s). To determine which

byte(s) have been written, the Z180 must read either LS or

MS locations and then repoll this bit. If only one location is

interrupting, the interrupt is cleared when that location is

read by the Z180.

Bit 0 FIFO Control Register Write (Read Only)

This bit is set when the PC/XT/AT writes to the FCR. This bit

is also set when Transmit occurs. It is reset when the Z180

MPU reads this register.

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