Z8018233FSC datasheet(24/109 Pages) ZILOG

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3-24

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

16550 MIMIC FIFO DESCRIPTION (Continued)

The PC interface may be interrupted when 1, 4, 8 or 14

bytes are available in the receiver FIFO by setting bits 6

and 7 in the FCR (FIFO Control Register, PC address 02H)

to the appropriate value. If the FIFO is not empty, but below

the above trigger value, a timeout interrupt is available if

the receiver FIFO is not written by the MPU or read by the

PC from an interval determined by the Character Timeout

Timer. This is an additional Timer with MPU access only

that is used to emulate the 16550 4 character timeout

delay.

The Receive FIFO timeout timers are designed to reload

and begin countdown after every read or write of the Rx

FIFO, regardless of the Rx trigger level or number of bytes

in the FIFO. Therefore, it is possible to get Timeout interrupts

more often than Receive data interrupts. In order to closely

emulate a 16550, a receive timeout timer enhancement is

provided. When enabling this feature, the timeout timer will

not begin counting down until the character emulation

timer for each byte of data in the Rx FIFO has expired.

Note: Enabling this feature will facilitate increased

16550 compatibility but may impede throughput. If the

Receive Timeout interrupt occurs, the PC HOST will only

be allowed to read up to 4-5 consecutive characters

before the Data Ready bit is forced to zero (even if there

is still more data in FIFO). This is required to maintain

character pacing.

16x8

Data Bits

Read

Pointer

ALU

Sync

Internal Clock

MPU

CNTL

Line

MPU

Databus

(MPU Side Read)

FIFO

Control

MPU

IRQ

Sync

PC Side

Databus

(PC Side Write)

Internal

Clock

IRQ

Cntrl

Line

Internal Clock

MPU Side

Interface

16550

MIMIC or

PC Side

Interface

Write

Pointer

The timer receives the ESCC /TRxCB as its input clock.

Software must determine the correct values to program

into the Receiver Timeout register and the ESCC TRxCB to

achieve the correct delay interval for timeout. These

interrupts are cleared by the FIFO reaching the trigger

point or by resetting the Timeout Interval Timer by FIFO

MPU write or PC read access.

With FIFO mode enabled, the MPU is interrupted when the

receiver FIFO is empty, corresponding to bit 5 being set

in the IUS/IP register (MPU access only). This bit

corresponds to a PC read of the receive buffer in non-FIFO

(16450) mode. The interrupt source is cleared when the

FIFO becomes non-empty or the MPU reads the IUS/IP

The transmitter FIFO is 16-byte FIFO with PC write and

MPU read access (Figure 8). In FIFO mode, the PC

receives an interrupt when the transmitter becomes empty

corresponding to bit 5 being set in the LSR. This bit and the

interrupt source are cleared when the transmit FIFO

becomes non-empty or the Interrupt Identification Register

(IIR) register is read by the PC.

Figure 8. 16550 MIMIC Transmitter FIFO Block Diagram

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