Z8018233FSC datasheet(62/109 Pages) ZILOG

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Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

PRELIMINARY

Zilog

DS971820600

INTERRUPT EDGE/PIN MUX REGISTER (Continued)

Bit 0. Programming this bit to 1 selects a 16 cycle wait

delay on recovery from HALT. Halt Recovery is disabled if

bit 5 of the enhancement register is set to 1. A 0 selects no

wait delay on Halt recovery.

If Halt Recovery is selected, the following pins assume the

following states during halt and during the recovery, whether

it is in HALT, SLP, IDLE or STBY Modes:

Address

= Z

Data Bus

= Z

MREQ/MRD

= Z

= 1

IORQ

= 1

BUSACK

= 1

RFSH

= 1

= Note 3

IOCS

= Z

MWR

= 1

(Note 4)

Notes:

1. This assumes that BUSREQ is not activated during the

halt.

2. This assumes that the refresh is not enabled. This would

not be a logical case since the address bus is tri-stated

during the Halt mode.

3. There is no control on the E line during the halt recovery

so transitions on the pin are possible.

4. This is only true if MWR function is enabled.

The Halt recovery mode is implemented by applying wait

states to the next CPU operation following the exit from

halt. All signals listed above are forced to their specified

state (unless otherwise noted) during halt and also during

the recovery state. Sixteen cycles after the halt pin goes

High the signals are released to their normal state, then

eight wait states are inserted to allow proper access to

accommodate slow memories.

After the first memory access, the wait states will be

inserted as programmed in the wait state generators.

In addition, if bit 4 of the Z80182 Enhancement Register is

set, the TxDA pin will be tri-stated during Halt and Recovery

modes.

Z8018233FSC 데이터시트(PDF) 62 Page - Zilog, Inc.

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