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Z8018233FSC 데이터시트(PDF) 97 Page - Zilog, Inc.

부품명 Z8018233FSC
상세설명  ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP??
PDF  109 Pages
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제조업체  ZILOG [Zilog, Inc.]
홈페이지  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8018233FSC 데이터시트(HTML) 97 Page - Zilog, Inc.

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3-97
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
PRELIMINARY
Zilog
DS971820600
Table D. Z85230 System Timing Table
20 MHz
No.
Symbol
Parameter
Min
Max
Notes [4]
1
TdRxC(REQ)
/RxC to /W//REQ Valid
13
18
[2]
2
TdRxC(W)
/RxC to /Wait Inactive
13
18
[1,2]
3
TdRxC(SY)
/RxC to /SYNC Valid
9
13
[2]
4
TdRxC(INT)
/RxC to /INT Valid
15
22
[1,2]
5
TdTxC(REQ)
/TxC to /W//REQ Valid
8
12
[3]
6
TdTxC(W)
/TxC to /Wait Inactive
8
15
[1,3]
7
TdTxC(DRQ)
/TxC to /DTR//REQ Valid
7
11
[3]
8
TdTxC(INT)
/TxC to /INT Valid
9
14
[1,3]
9
TdSY(INT)
/SYNC to /INT Valid
2
6
[1]
10
TdExT(INT)
/DCD or /CTS to /INT Valid
3
9
[1]
Notes:
These AC parameters values are preliminary and subject to change without notice.
[1] Open-drain output, measured with open-drain test load.
[2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[4] Units equal to TcPc
Table E. I/O Port Timing
Z8L182
Z80182
20 MHz
33 MHz
No.
Symbol
Parameter
Min
Max
Min
Max
1
TsPIA(RD)
Port Data Input Setup to /RD Fall
20
20
2
ThPIA(RD)
Port Data Input Hold From /RD Rise
0
0
3
TdWR
F(PIA)
Port Data Output Delay From /WR Fall
60
60
4T
FWRF(PIA)
Port Data Output Float From /WR Fall
0
0
Table F. External Bus Master Timing
Z8L182
Z80182
20 MHz
33 MHz
No.
Symbol
Parameter
Min
Max
Min
Max
1
TsA(IORQf)
Address to /IORQ Fall Setup
10
5
2
TsIOf(WRf)
/IORQ Fall to /WR Fall Setup
0
0
3
TsIOf(RDf)
/IORQ Fall to /RD Fall Setup
0
0
4
ThIOR(WR
R)
/IORQ Rise From /WR Rise Hold
0
0
5
ThIOR(RD
R)
/IORQ Rise From /RD Rise Hold
0
0
6
TdRDf(DO)
/RD Fall to Data Out Valid Delay
50
45
7T
HRDR(DO)
/RD Rise to Data Out Valid Hold
0
0
8T
SD(WRR)
Data In to /WR Fall Setup
50
50
9
THD(WR
R)
Data In From /WR Rise Hold
10
8
10



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