SIO1007 datasheet(51/108 Pages) MICROCHIP

51 / 108 page

 2005 - 2015 Microchip Technology Inc.

DS00002020A-page 51

SIO1007

15.0

SYSTEM MANAGEMENT INTERRUPT (SMI)

The SIO1007 implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt

with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists of

the enabled interrupts from Super I/O Device Interrupts (Serial Port 1 and 2) and many of the GPIOs pins. The

GP12/nIO_SMI pin, when selected for the nIO_SMI function, can be programmed to be active high or active low via bit

2 in the GPIO Polarity Register 1 (CR32). The nIO_SMI pin function defaults to active low. The output buffer type of the

pin can be programmed to be open-drain or push-pull via GPIO Output Type Register (CR39).

The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2. The nSMI output is then

enabled onto the nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be enabled onto

the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2.

15.1

SMI Registers

The SMI event bits for the GPIOs events are located in the SMI status and Enable registers 1 and 2. The polarity of the

edge used to set the status bit and generate an SMI is controlled by the GPIO Polarity Registers located in the Config-

uration section. For non-inverted polarity (default) the status bit is set on the low-to-high edge. Status bits for the GPIOs

are cleared on a write of ‘1’.

The SMI logic for the GPIO events is implemented such that the output of the status bit for each event is combined with

the corresponding enable bit in order to generate an SMI.

The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these status

bits are cleared at the source; these status bits are not cleared by a write of ‘1’. The SMI logic for these events is imple-

mented such that each event is directly combined with the corresponding enable bit in order to generate an SMI.

See the Runtime Registers section for the definition of the SMI status and enable registers.

SIO1007 데이터시트(PDF) 51 Page - Microchip Technology