SIO1007 datasheet(56/108 Pages) MICROCHIP

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SIO1007

DS00002020A-page 56

 2005 - 2015 Microchip Technology Inc.

Note 17-2

Although the bits in this runtime register default at VTR POR to ‘0’, the value read is affected by the

GPIO pin state. Each GPIO pin’s state at VCC POR is controlled by the pin’s programmed

configuration and the external interface (e.g. input driven low by external device.) Each GPIO pin has

programmable configuration bits in CR31-CR39 which control direction, output types, polarity, and

internal pull-ups. For example, the GPIO internal pull-ups are controlled by CR37 and CR38 and

default at VTR POR to pull-up enabled (logic ‘1’). If not reprogrammed any open input will have logic

‘1’ at VCC POR. This will affect this runtime register.

SMI_EN1

Default = 0x00

on VTR POR

(R/W)

SMI Enable Register 1

This register is used to enable the different interrupt sources onto the internal

group nSMI signal.

1=Enable

0=Disable

Bit[0] GP10

Bit[1] GP11

Bit[2] GP12

Bit[3] GP13

Bit[4] GP14

Bit[5] GP15

Bit[6] GP16

Bit[7] GP17

SMI_EN2

Default = 0x00

on VTR POR

(R/W)

SMI Enable Register 2

This register is used to enable the different interrupt sources onto the internal

group nSMI signal, and the internal group nSMI signal onto the nIO_SMI

GPI/O pin or the serial IRQ stream on IRQ2.

1=Enable

0=Disable

Bit[0] Reserved

Bit[1] EN_U2INT

Bit[2] EN_U1INT

Bit[3] EN_CIRCC2

Bit[5:4] Reserved

Bit[6] EN_SMI_S (Enable group nSMI signal onto serial IRQ2)

Bit[7] EN_SMI (Enable group nSMI signal onto IO_SMI# pin)

GP1

Default = 0x00

on VTR POR

See Note 17-2

R/W

General Purpose I/O Data Register 1

Bit[0]GP10

Bit[1]GP11

Bit[2]GP12

Bit[3]GP13

Bit[4]GP14

Bit[5]GP15

Bit[6]GP16

Bit[7]GP17

GP2

Default = 0x00

on VTR POR

Bit[7:0]Reserved

GP3

Default = 0x00

on VTR POR

See Note 17-2

R/W

General Purpose I/O Data Register 3

Bit[0]GP30

Bit[1]GP31

Bit[2]GP32

Bit[3]GP33

Bit[4]GP34

Bit[5]GP35

Bit[6]GP36

Bit[7]GP37

GP4

Default = 0x00

on VTR POR

Bit[7:0]Reserved

Note:

Reserved bits return 0 on read.

TABLE 17-2:

RUNTIME REGISTERS BLOCK DESCRIPTION (CONTINUED)

Name/Default

Offset

Description

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