SIO1007 datasheet(84/108 Pages) MICROCHIP

84 / 108 page

SIO1007

DS00002020A-page 84

 2005 - 2015 Microchip Technology Inc.

Note 18-9

The Activate bit disables the selected address range for the logical device. When the Activate bit is

set and the corresponding Logical Device resides at a valid I/O base address, the Logical Device will

participate in Plug-and-Play range checking.

APPLICATION NOTE: When the Activate bit (CR3A bit 3 to ‘1’), the values in CR3B and CR3C must be valid;

otherwise, an undefined state and undesired behavior may result.

18.4.58

CR3B-3C

CR3B can only be accessed in the configuration state and after the CSR has been initialized to 3BH. CR3C can only

be accessed in the configuration state and after the CSR has been initialized to 3CH.

CR3B and CR3C are used to

select the base address of LPC Docking. Valid addresses for LPC Docking runtime register space can be set to locations

on single -byte boundaries from 0000H - FFFFH. To disable LPC Docking runtime register decoding, set the Activate bit

(CR3A-bit 3 to ‘0’).

Set CR3A-bit 3 to ‘0’ (to disable LPC Docking runtime register decoding) when writing the LPC Docking Base Address

registers CR3B and CR3C.

The LPC Docking runtime register uses full 16-bit addressing decoding.

3LPC Dock

Note 18-9

A high level on this bit, enables the host access to LPC Docking logical

device’s I/O runtime register space. The I/O address is selected by the LPC

Docking Base Address Registers.

A low level on this bit disables the host access to LPC Docking logical

device (default).

4,5,6, 7

Reserved

Read Only. A read returns 0

TABLE 18-52: CR3B

LPC Docking Base Address Register High Byte

Type: R/W

Default: 0X00 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

ADR8

LPC Docking Base Address bits for decoder.

ADR9

ADR10

ADR11

ADR12

ADR13

ADR14

ADR15

TABLE 18-51: CR3A (CONTINUED)

Logical Device Activate Register

Type: R/W

Default: 0x00 on VCC POR

BIT NO.

BIT NAME

DESCRIPTION

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