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SIO1007 데이터시트(PDF) 86 Page - Microchip Technology |
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SIO1007 데이터시트(HTML) 86 Page - Microchip Technology |
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86 / 108 page ![]() SIO1007 DS00002020A-page 86 2005 - 2015 Microchip Technology Inc. Note 18-10 The Configuration Port is at either 0x002E, 0x004E, 0x162E or 0x164E (controlled by the SYSOPT[1:0] Strap options) at power up and can be relocated via CR12 and CR13. Note 18-11 The UART and IR Power Register at CR02 Power Control bits disable the respective logical device and associated pins, however the power control bit does not disable the selected address range for the logical device. To disable the host address registers software must clear the activate bits in CR3A, the Logical Device Activate Register. Devices that are powered down and still activated will participate in Plug-and-Play range checking. Config. Port CR12 - CR13 See Note 18-10 [0x0000:0x07FE] On 2-byte boundaries See Configuration Registers in Table 18- 3. They are accessed through the index and DATA ports located at the Configuration Port address and the Configuration Port address +1 respectively. LPC Docking CR3B-3C See Note 18-9 on page 84 [0x0000:0x0FFF] On single byte boundaries +0 : Docking LPC Switch Register TABLE 18-54: I/O BASE ADDRESS CONFIGURATION REGISTER DESCRIPTION (CONTINUED) Logical Device Register Index Base I/O Range Fixed Base Ofsets |
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