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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP320C2811PBKA 데이터시트(PDF) 116 Page - Texas Instruments |
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TMP320C2811PBKA 데이터시트(HTML) 116 Page - Texas Instruments |
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116 / 147 page  Electrical Specifications 116 June 2004 SPRS257 6.23 External Interface Read Timing Table 6−26. External Memory Interface Read Switching Characteristics PARAMETER MIN MAX UNIT td(XCOH-XZCSL) Delay time, XCLKOUT high to zone chip-select active low 1 ns td(XCOHL-XZCSH) Delay time, XCLKOUT high/low to zone chip-select inactive high −2 3 ns td(XCOH-XA) Delay time, XCLKOUT high to address valid 2 ns td(XCOHL-XRDL) Delay time, XCLKOUT high/low to XRD active low 1 ns td(XCOHL-XRDH Delay time, XCLKOUT high/low to XRD inactive high −2 1 ns th(XA)XZCSH Hold time, address valid after zone chip-select inactive high † ns th(XA)XRD Hold time, address valid after XRD inactive high † ns † During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles. Table 6−27. External Memory Interface Read Timing Requirements MIN MAX UNIT ta(A) Access time, read data from address valid (LR + AR) − 14‡ ns ta(XRD) Access time, read data valid from XRD active low AR − 12‡ ns tsu(XD)XRD Setup time, read data valid before XRD strobe inactive high 12 ns th(XD)XRD Hold time, read data valid after XRD inactive high 0 ns ‡ LR = Lead period, read access. AR = Active period, read access. See Table 6−24. Lead Active Trail DIN td(XCOHL-XRDL) td(XCOH-XA) td(XCOH-XZCSL) td(XCOHL-XRDH) th(XD)XRD td(XCOHL-XZCSH) XCLKOUT=XTIMCLK XCLKOUT=1/2 XTIMCLK XZCS0AND1, XZCS2, XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals will transition to their inactive state. C. For USEREADY = 0, the external XREADY input signal is ignored. D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles. tsu(XD)XRD ta(A) ta(XRD) XREADY Figure 6−26. Example Read Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE ≥1 ≥0 ≥0 0 0 N/A† N/A† N/A† N/A† † N/A = “Don’t care” for this example |
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