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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP320C2811PBKA 데이터시트(PDF) 117 Page - Texas Instruments |
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TMP320C2811PBKA 데이터시트(HTML) 117 Page - Texas Instruments |
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117 / 147 page  Electrical Specifications 117 June 2004 SPRS257 6.24 External Interface Write Timing Table 6−28. External Memory Interface Write Switching Characteristics PARAMETER MIN MAX UNIT td(XCOH-XZCSL) Delay time, XCLKOUT high to zone chip-select active low 1 ns td(XCOHL-XZCSH) Delay time, XCLKOUT high or low to zone chip-select inactive high −2 3 ns td(XCOH-XA) Delay time, XCLKOUT high to address valid 2 ns td(XCOHL-XWEL) Delay time, XCLKOUT high/low to XWE low 2 ns td(XCOHL-XWEH) Delay time, XCLKOUT high/low to XWE high 2 ns td(XCOH-XRNWL) Delay time, XCLKOUT high to XR/W low 1 ns td(XCOHL-XRNWH) Delay time, XCLKOUT high/low to XR/W high −2 1 ns ten(XD)XWEL Enable time, data bus driven from XWE low 0 ns td(XWEL-XD) Delay time, data valid after XWE active low 4 ns th(XA)XZCSH Hold time, address valid after zone chip-select inactive high † ns th(XD)XWE Hold time, write data valid after XWE inactive high TW−2‡ ns tdis(XD)XRNW Data bus disabled after XR/W inactive high 4 ns † During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles. ‡ TW = Trail period, write access. See Table 6−24. Lead Active Trail td(XCOH-XZCSL) td(XCOH-XA) td(XCOHL-XWEL) td(XCOHL-XWEH) td(XCOHL-XZCSH) ten(XD)XWEL th(XD)XWEH tdis(XD)XRNW XCLKOUT=XTIMCLK XCLKOUT=1/2 XTIMCLK XZCS0AND1, XZCS2, XZCS6AND7 XA[0:18] XRD XWE XR/W XD[0:15] NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals will transition to their inactive state. C. For USEREADY = 0, the external XREADY input signal is ignored. D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles. td(XCOH-XRNWL) td(XCOHL-XRNWH) DOUT XREADY td(XWEL-XD) Figure 6−27. Example Write Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE N/A† N/A† N/A† 0 0 ≥1 ≥0 ≥0 N/A† † N/A = “Don’t care” for this example |
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