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TMS320DM355CZCEA13 데이터시트(PDF) 130 Page - Texas Instruments

부품명 TMS320DM355CZCEA13
상세설명  Digital Media System-on-Chip (DMSoC)
PDF  163 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320DM355CZCEA13 데이터시트(HTML) 130 Page - Texas Instruments

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VCLKIN(A)
(Positive Edge Clocking)
9
VCLKIN(A)
(Negative Edge Clocking)
10
VCTL(B)
A. VCLKIN=PCLKorEXTCLK
B. VCTL=HSYNC,VSYNC,andFIELD
VCLKIN(A)
(Positive Edge Clocking)
13
VCLKIN(A)
(Negative Edge Clocking)
11
VCTL(B)
A. VCLKIN=PCLKorEXTCLK
B. VCTL=HSYNC,VSYNC,FIELD,andLCD_OE
C. VDATA=COUT[7:0],YOUT[7:0],R[7:3],G[7:2],andB[7:3]
VDATA(C)
14
12
TMS320DM355
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
www.ti.com
Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK
Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and EXTCLK(1) (2) (3) (see Figure 5-29)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
11
td(VCLKIN-VCTLV)
Delay time, VCLKIN edge to VCTL valid
13.3
ns
12
td(VCLKIN-VCTLIV)
Delay time, VCLKIN edge to VCTL invalid
2
ns
13
td(VCLKIN-VDATAV)
Delay time, VCLKIN edge to VDATA valid
13.3
ns
14
td(VCLKIN-VDATAIV)
Delay time, VCLKIN edge to VDATA invalid
2
ns
(1)
The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.
(2)
VCLKIN = PCLK or EXTCLK
(3)
VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK
130
DM355 Peripheral Information and Electrical Specifications
Copyright © 2007–2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM355



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