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Revision 1.07

HFCG Control Register 1 (HFCGCTRL1)

The HFCGCTRL1 register sets the frequency multiplier’s operating parameters. On VCC power-up, WATCHDOG reset and

Debugger Interface reset, it is initialized to 0C16.

Location: 00 FFA016

Type: Varies per bit

Bit

76543210

Name

Reserved

FAST96

LOAD96

IVLID

OHFC

PENABLE

FAST

LOAD

Reset

00001100

Bit

Type

Description

0WO

LOAD (Load M and N Values). Write 1 to this bit to perform a normal frequency change by loading

the HFCGML, HFCGMH and HFCGN buffer data to the frequency multiplier. The pre-scaler is

automatically set to a divide by 1. The bit always reads back 0. Results are undefined when more than

one of the following bits is written with 1 at the same time: LOAD, FAST, LOAD96, FAST96.

1WO

FAST (Load M, N and I Values). Write 1 to this bit to perform a fast frequency change by loading the

HFCGML, HFCGMH, HFCGN, HFCGIH and HFCGIL input buffer data in the frequency multiplier. The

pre-scaler is automatically set to a divide by 1. The bit always reads back 0. Results are undefined when

more than one of the following bits is written with 1 at the same time: LOAD, FAST, LOAD96, FAST96.

2RO

PMC ENABLE (Enable Core Domain Clock). Provides the status of the PMC enable/disable

command. Any data written to this bit is ignored.

0: Disabled

1: Enabled

3RO

OHFC (Output Clock Status). Indicates when the HFCG is oscillating and produces a stable clock.

Any data written to this bit is ignored.

0: Not oscillating

1: Oscillating with stable output

4RO

IVLID (I Value Valid).

0: Data read is invalid; repeat HFCGIL register read operation

1: Data read is valid; HFCGIH can be read

5WO

LOAD96 (Load M and N Values for 96 MHz). Write 1 to this bit to perform normal locking on 96 MHz

frequency by loading the hardwired variables M and N to the frequency multiplier. The pre-scaler is set

according to the value held in HFCGP register. The bit always reads back 0. Results are undefined

when more than one of the following bits is written with 1 at the same time: LOAD, FAST, LOAD96,

FAST96.

6WO

FAST96 (Load M, N and I Values for 96 MHz). Write 1 to this bit to perform fast locking on 96 MHz

frequency by loading the hardwired variables M and N and registers HFCGIH and HFCGIL to the

frequency multiplier. The pre-scaler is set according to the value held in HFCGP register. The bit

always reads back 0. Results are undefined results when more than one of the following bits is written

with 1 at the same time: LOAD, FAST, LOAD96, FAST96.

Reserved.

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