PC87591L datasheet(248/437 Pages) NSC

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Embedded Controller Modules (Continued)

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4.19 THE DEBUGGER INTERFACE

The Debugger Interface module links between a debugger running on a host machine and the PC87591x.

The Debugger interface associates a processor number with the processor core. The number associated with the core is 0.

The Debugger interface can also program the on-chip flash.

4.19.1 Features

●

Debugger communication via an IEEE 1149.1b 1994 JTAG serial bus

●

Test Access Port (TAP) for JTAG serial bus

●

Hardware reset signal assertion by debugger command

●

Conﬁgurable ABORT event

●

Interrupt signal (TINT) to the debugger indicates a waiting message

●

Waiting message to on-chip processor by non-maskable ISE interrupt

●

8-word (16-byte) Rx (downstream) data link

●

8-word (16-byte) Tx (upstream) data link

●

On-chip ﬂash support

— Read, Program and Erase

— Read protect option to secure contents

4.19.2 Structure

The Debugger interface consists of a TAP, ISE Interrupt Control, Rx and Tx data links and a PC87591x reset-by-command

source circuit. Figure 80 shows these functional blocks.

Figure 80. Debugger Interface

Rx Data

Peripheral Bus

Tx Data

ISE Interrupt

Control

TAP

JTAG Serial Bus

TINT

ISE

Interrupts

Debugger

Reset

Link

Flash Programing

Interface

Flash

On-Chip

Reset Circuit

and Flash

PC87591L 데이터시트(PDF) 248 Page - National Semiconductor (TI)

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