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PC87591L 데이터시트(PDF) 262 Page - National Semiconductor (TI) |
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PC87591L 데이터시트(HTML) 262 Page - National Semiconductor (TI) |
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262 / 437 page ![]() Embedded Controller Modules (Continued) www.national.com 262 Revision 1.07 4.19.8 TAP Data Registers, Flash Interface This section describes the flash interface registers available to the host through the flash interface. The bit ordering is as described in “TAP Data Registers, Debugger Interface” on page 260. Flash Control and Status Register (FL_CT_ST) FL_CT_ST is a shift register that enables reading from the Flash Status register and writing to the Flash Control register. The Flash Status register is read in Capture-DR state; the Flash Control register is updated in Update-DR state. The con- nection of the register to the serial chain is shown in Figure 87. The Control and Status registers are reset at Power-Up and TAP resets only. Flash Status Type: Varies per bit Bit 76543210 Name FMPRGE BLFF FLAEN FMDERR FMBFULL FMBUSY FMPERR FMEERR Reset 00000100 Bit 15 14 13 12 11 10 9 8 Name JTFIE DISVRF Reserved FMSPERE FMSERE FMPERE Reset 00000000 Bit Type Description 0 R/W1C FMEERR (Flash Memory Erase Error). Indicates an error in erasing to the flash. It is cleared by writing 1 to FMEERR bit in the Control register. This bit may be cleared only when FMBUSY bit is cleared (0). 0: No program error detected (default) 1: An error occurred during erase This bit may be cleared only when FMBUSY bit is cleared (0). 1 R/W1C FMPERR (Flash Memory Program Error). Indicates an error in writing to the flash. It is cleared by writing 1 to FMPERR bit in the Control register. This bit may be cleared only when FMBUSY bit is cleared (0). 0: No program error detected (default) 1: An error occurred during program 2RO FMBUSY (Flash Memory Busy). 0: The embedded flash is ready to accept operations if no error flag is set 1: The embedded flash is not accessible because the PC87591x clocks are not ready or the embedded flash is busy programing or erasing 3RO FMBFULL (Flash Double-Buffer Full). 0: There is at least one empty word in the flash double buffer 1: The double-buffer is full Figure 87. Flash Control and Status Register 15 0 TDI TDO Flash Control Status 15 0 FL_CR_ST |
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