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PC87591L 데이터시트(PDF) 264 Page - National Semiconductor (TI) |
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PC87591L 데이터시트(HTML) 264 Page - National Semiconductor (TI) |
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264 / 437 page ![]() Embedded Controller Modules (Continued) www.national.com 264 Revision 1.07 Flash Address Register (FL_ADDR) FL_ADDR is a shift register that enables reading from and writing to flash addresses. The address includes two fields: the Flash Address and the Block Identifier (main block or information block). In Capture-DR state, the next address for read and/or program is read. In case of a program or page erase fail, the offset within the section of the failing memory location is returned. In Update-DR state, the address register is loaded with a new address. The connection of the register to the serial chain is shown in Figure 89. The address register is reset at Power-Up and TAP resets only. Type: R/W Bit Description 7-0 SID (SuperI/O Identification). Returns the value of SID register (see “SuperI/O ID Register (SID)” on page 344) 15-8 SRID (SuperI/O Revision ID). Returns the value of SID register (see “SuperI/O Revision ID Register (SRID)” on page 346) 31-16 Reserved. Bit 31 30 29 28 27 26 25 24 23 2 21 20 19 18 17 16 15 14 13 12 11 10 9 876543210 Name Block ID Flash Address Reset 0 0 Bit Type Description 27-0 R/W Flash Address. Holds the flash address in bytes, starting from address 0000016. The flash last address depends on the block size. All addresses must be word aligned. Note that the field may hold values larger than the actual flash size. Addresses beyond the flash size are reserved and should not be specified. 31-28 R/W Block ID. Holds an ID for a specific block. The ID field values are: Bits 31 30 29 28 Description 0 0 0 0: For Capture-DR, reserved; for Update-DR, no load of Address and Block ID registers (default) 0 0 0 1: Flash Main Block 0 0 1 0: Flash Information Block Other: Reserved Figure 89. Flash Address Register 0 TDI TDO Flash Address 27 0 FL_ADDR Block ID 30 31 |
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