PC87591L datasheet(303/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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5.3.6

Random Number Generator (PC87591S)

The PC87591S includes a Random Number Generator unit. Once enabled, this unit can provide up to 800 random bits per

second. The random bits may be read one byte at a time from RNGD register when DVALID bit in RNGCS register is set.

Note that a double buffer scheme is used to improve the performance of bit gathering. The randomization of the data is ver-

ified by compliance with FIPS140-1 specifications.

5.3.7

Signaling Interface

For memory update operations, the host may need to exchange signals (indicating the state) with the core. The Signaling

interface supports this scheme. The scheme is designed mainly for polling-based operations, but it allows the host to inter-

rupt the core.

The signaling hardware includes an 8-bit register that may be read by both host and core. The host may modify bits 0 through

3 of this register; the core may modify bits 4 through 7. A host write to the register sets the Host Semaphore Write (HSEMW)

bit in the Shared Memory Core Control and Status register (SMCCST); if the interrupt enable bit (HSEMIE in SMCCST reg-

ister) is set, the shared memory interrupt to the core is set.

5.3.8

Shared Memory Host Registers

The following set of registers is accessible only by the host. The registers are maintained by VDD.

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

Shared Memory Host Register Map

Offset

Mnemonic

Type

0016

SMIMA0

Shared Memory Indirect Memory Address 0

R/W

0116

SMIMA1

Shared Memory Indirect Memory Address 1

R/W

0216

SMIMA2

Shared Memory Indirect Memory Address 2

R/W

0316

SMIMA3

Shared Memory Indirect Memory Address 3

R/W

0416

SMIMD

Shared Memory Indirect Memory Data

R/W

0516

SMHC

Shared Memory Host Control

R/W

0616

SMHST

Shared Memory Host Status

Varies per bit

0716

SMHAP1

Shared Memory Host Access Protect 1

Varies per bit

0816

SMHAP2

Shared Memory Host Access Protect 2

Varies per bit

0C16

SMHSEM

Shared Memory Host Semaphore

Varies per bit

Figure 103. Signaling Interface

HSEM(3-0)

CSEM(3-0)

Host Side

HSEMW

Writes

Core Side

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