PC87591L datasheet(305/437 Pages) NSC

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Host Controller Interface Modules (Continued)

Revision 1.07

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Shared Memory Indirect Memory Data Register (SMIMD)

This register defines data bits 7-0 for a read or write transaction to the memory.

Location: Offset 0416

Type: R/W

Shared Memory Host Control Register (SMHC)

This register controls the embedded flash operation modes for host-initiated transactions. The register is cleared (0016)on

Host Domain Hardware reset.

Location: Offset 0516

Type: R/W

Shared Memory Host Status Register (SMHST)

This register provides the embedded flash status for host initiated transactions. The register is cleared (0016) on Host Do-

main Hardware reset.

Location: Offset 0616

Type: Varies per bit

Bit

76543210

Name

Indirect Memory Data 7-0

Bit

Description

7-0

Indirect Memory Data 7-0.

Bit

76543210

Name

Reserved

PMER

Reserved

Reset

00000000

Bit

Description

4-0

Reserved.

PMER (Page Erase). When the bit is set (1), a valid host write to the embedded flash erases the entire page

pointed to by the write address.

This bit can be altered only when HBUSY bit is cleared (0); otherwise results are undeﬁned.

7-6

Reserved.

Bit

76543210

Name

Reserved

HDERR

FMLFULL

HBUSY

HPERR

HEERR

Reset

00000000

Bit

Type

Description

R/W1C HEERR (Host Erase Error). The bit is set (1) when an error occurs during a host-initiated erase. The

bit is cleared by writing 1 to it.

This bit can be cleared only when HBUSY bit is cleared (0).

R/W1C HPERR (Host Program Error). The bit is set (1) when an error occurs during a host-initiated program.

The bit is cleared by writing 1 to it.

This bit can be cleared only when HBUSY bit is cleared (0).

2RO

HBUSY (Host Busy). Read only. The bit is set (1) when the embedded ﬂash is busy programing or

erasing the flash due to a host-initiated operation.

3RO

FMLFULL (Double Buffer Full). Read only. The bit is set (1) when the double buffer is full.

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