PC87591L datasheet(404/437 Pages) NSC

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7.0 Device Specifications (Continued)

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404

Revision 1.07

7.6.14 USART Timing

Figure 162. USART Asynchronous Mode Timing

Symbol

Figure

Description

Reference Conditions

Min

Max

Unit

162

CMOS output rise time.

Note 1

1. Not tested; guaranteed by characterization.

6ns

162

CMOS output fall time.

Note 1

6ns

tCOh2

163

Output hold (synchr. mode)

After RE USCLK

−(2t

CLK

+10 ns)

tCOv2

163

Output valid (synchr. mode)

After RE USCLK

2tCLK

+10 ns

tCOh

162

Output hold (synchr. mode)

After RE USCLK

−20

tIs

162

Input setup time

(asynchr. mode)

Before RE CLK

tIh

162

Input hold time

(asynchr. mode)

After RE CLK

tCLKX

162

USCLK input period (synchr.

mode)

250

tCLKh

162

USCLK input low time.

2tCLK

tCLKl

162

USCLK input high time.

2tCLK

tSIs

163

Input Setup time (synchr.

mode)

Before FE USCLK (in)

in synchronous mode

tCLK +

10 ns

tSIh

163

Input Hold time (synchr.

mode)

After FE USCLK (in)

in synchronous mode

tCLK +

10 ns

tSIs1

164

Input Setup time (synchr.

mode)

Before FE USCLK (out)

in synchronous mode

tSIh1

164

Input Hold time (synchr.

mode)

After FE USCLK (out)

in synchronous mode

CLK

COv

Output Signals:

UTXD

USCLK

Input Signals:

URXD

USCLK (In)

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