PC87591L datasheet(160/437 Pages) NSC

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Revision 1.07

Mode Select Register (UMDSL)

This byte-wide read/write register controls the selection of the clock source, Synchronous mode, Attention mode and line

break generation. It contains the enable bits for the DMA channels. The register is cleared (0016) on reset.

Location: 00 FD2A16

Type: R/W

Bit

76543210

Name

Reserved

ERD

ETD

CKS

BRK

ATN

MOD

Reset

00000000

Bit

Description

MOD. Selects the Synchronous or Asynchronous mode of operation:

0: Asynchronous mode

1: Synchronous mode

ATN. Selects the Attention mode of operation. Cleared by hardware after reception of an address frame that is

a 9-bit character with a “1” in the ninth bit position.

0: Disable Attention mode

1: Enable Attention mode

BRK. Setting the bit (1) causes UTXD to go low. UTXD remains low until the bit is cleared (0) by the user.

CKS. Controls the source of the clock while operating in Synchronous mode (MOD=1).

0: USART operates from the baud rate generator and outputs the baud rate clock on USCLK

1: USART operates from an external clock provided on USCLK

While the USART is operated in Asynchronous mode (MOD=0), the bit has no effect.

ETD.

0: No DMA request is asserted for transmit operations

1: DMA request is asserted when the Transmit Buffer Empty (TBE) flag is set (1)

ERD.

0: No DMA request is asserted for receive operations

1: DMA request is asserted when the Receive Buffer Full (RBF) flag is set (1)

7-6

Reserved.

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