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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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GXM 데이터시트(PDF) 44 Page - National Semiconductor (TI) |
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GXM 데이터시트(HTML) 44 Page - National Semiconductor (TI) |
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44 / 244 page  www.national.com 44 Revision 3.1 Processor Programming (Continued) 3.3.2 System Register Set The system register set, shown in Table 3-5, consists of registers not generally used by application programmers. These registers are typically employed by system level programmers who generate operating systems and mem- ory management programs. Associated with the system register set are certain tables and segments which are listed in Table 3-5. The Control Registers control certain aspects of the GXm processor such as paging, coprocessor functions, and segment protection. The Descriptor Tables hold descriptors that manage memory segments and tables, interrupts and task switch- ing. The tables are defined by corresponding registers. The two Task State Segments Tables defined by TSS reg- ister are used to save and load the computer state when switching tasks. The Configuration Registers areusedtodefinethe GXm CPU setup including cache management. The ID registers allow BIOS and other software to identify the specific CPU and stepping. System Management Mode (SMM) control information is stored in the SMM reg- isters. The Debug Registers provide debugging facilities for the GXm processor and enable the use of data access break- points and code execution breakpoints. The Test Registers provide a mechanism to test the con- tents of both the on-chip 16 KB cache and the Translation Lookaside Buffer (TLB). The TLB is used as a cache for the tables that are used in to translate linear addresses to physical addresses while paging is enabled. Table 3-5 lists the system register sets along with their size and function. Table 3-5. System Register Set Group Name Function Width (Bits) Control Registers CR0 System Control Register 32 CR2 Page Fault Linear Address Register 32 CR3 Page Directory Base Register 32 CR4 Time Stamp Counter 32 Descriptor Tables GDT General Descriptor Table 32 IDT Interrupt Descriptor Table 32 LDT Local Descriptor Table 16 Descriptor Table Registers GDTR GDT Register 32 IDTR IDT Register 32 LDTR LDT Register 16 Task State Segment and Registers TSS Task State Segment Tables 16 TR TSS Register Setup 16 Configuration Registers CCRn Configuration Control Registers 8 ID Registers DIRn Device Identification Registers 8 SMM Registers SMARn SMM Address Region Registers 8 SMHRn SMM Header Addresses 8 Performance Registers PCR0 Performance Control Register 8 Debug Registers DR0 Linear Breakpoint Address 0 32 DR1 Linear Breakpoint Address 1 32 DR2 Linear Breakpoint Address 2 32 DR3 Linear Breakpoint Address 3 32 DR6 Breakpoint Status 32 DR7 Breakpoint Control 32 Test Registers TR3 Cache Test 32 TR4 Cache Test 32 TR5 Cache Test 32 TR6 TLB Test Control 32 TR7 TLB Test Status 32 |
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