GXM datasheet(79/244 Pages) NSC

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Processor Programming (Continued)

3.11.1 SMM Enhancements

Eight SMM instructions have been added to the x86

instruction set that permit initiating SMM through software

andsavingand restoring the total CPU statewhenin

SMM.

The SMM header now:

• Stores 32-bits memory addresses.

• Stores 32-bit memory data.

• Differentiates memory and I/O accesses.

• Indicates if an SMM interrupt was generated by access

to a VGA region.

The SMM service code is now cacheable. An SMAR reg-

ister specifies the SMM region code base and limit. An

SMHR register specifies the physical address for the

SMM header. The SMI_NEST bit enables the nesting of

SMM interrupts.

3.11.2 SMM Operation

SMM execution flow is summarized in Figure 3-10. Enter-

ing SMM requires the assertion of the SMI# pin for at least

two SYSCLK periods or execution of the SMINT instruction.

For the SMI# signal or SMINT instruction to be recog-

nized, configuration register bits must be set as shown in

Table 3-34. (The configuration registers are discussed in

detail in Section 3.3.2.2 “Configuration Registers” on page

47.)

After triggering an SMM through the SMI# pin or a SMINT

instruction, selected CPU state information is automati-

cally saved in the SMM memory space header located at

the top of SMM memory space. After saving the header,

the CPU enters real mode and begins executing the SMM

service routine starting at the SMM memory region base

address.

The SMM service routine is user definable and may con-

tain system or power management software. If the power

management software forces the CPU to power down or if

the SMM service routine modifies more registers than are

automatically saved, the complete CPU state information

should be saved.

Figure 3-10. SMM Execution Flow

Table 3-34. SMI# and SMINT Recognition

Requirements

SMI#

SMINT

USE_SMI, CCR1[1] (Index C1h)

SMAC, CCR1[2] (Index C1h)

SIZE[3:0], SMAR3[3:0] (Index CFh)

> 0

SMI# Sampled Active or

SMINT Instruction Executed

CPU State Stored in SMM

Address Space Header

Program Flow Transfers

to SMM Address Space

CPU Enters Real Mode

Execution Begins at SMM

Address Space Base Address

RSM Instruction Restores CPU

State Using Header Information

Normal Execution Resumes

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