GXM datasheet(99/244 Pages) NSC

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Integrated Functions (Continued)

4.1.6

CPU_READ/CPU_WRITE Instructions

The GXm processor has several internal registers that

control the BLT buffer and power management circuitry in

the dedicated cache subsystem. To avoid adding addi-

tional instructions to read and write these registers, the

GXm processor has a general mechanism to access inter-

nal CPU registers with reasonable performance. The

GXm processor has two special instructions to read and

write CPU registers: CPU_READ and CPU_WRITE. Both

instructions fetch a 32-bit register address from EBX as

showninTable4-7 andTable4-8. CPU_WRITE uses EAX

for the source data, and CPU_READ uses EAX as the

destination. Both instructions always transfer 32 bits of

data.

These instructions work by initiating a special I/O transac-

tion where the high address bit is set. This provides a very

large address space for internal CPU registers.

The BLT buffer base registers define the starting physical

addresses of the BLT buffers located within the dedicated

L1 cache. The dedicated cache can be configured for up

to 4 KB, so 12 address bits are required for each base

address.

Table 4-7. CPU-Access Instructions

Syntax

Opcode

Registers

Length

CPU_WRITE

0F3Ch

EBX = 32-bit address, EAX = Source

2 bytes

CPU_READ

0F3Dh

EBX = 32-bit address, EAX = Destination

2 bytes

Table 4-8. Address Map for CPU-Access Registers

EBX Address

Description

L1_BB0_BASE

FFFFFF0Ch

BLT Buffer 0 base address (see Table 4-4 on page 96).

L1_BB1_BASE

FFFFFF1Ch

BLT Buffer 1 base address (see Table 4-4 on page 96).

L1_BB0_POINTER

FFFFFF2Ch

BLT Buffer 0 pointer address (see Table 4-4 on page 96).

L1_BB1_POINTER

FFFFFF3Ch

BLT Buffer 1 pointer address (see Table 4-4 on page 96).

PM_BASE

FFFFFF6Ch

Power management base address (see Table 6-3 on page 181).

PM_MASK

FFFFFF7Ch

Power management address mask (see Table 6-3 on page 181).

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