GXM datasheet(89/244 Pages) NSC

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Processor Programming (Continued)

3.15 FLOATING POINT UNIT OPERATIONS

The FPU is x87-instruction-set compatible and adheres to

the IEEE-754 standard. Because most applications that

contain FPU instructions intermix with integer instructions,

the GXm processor’s FPU achieves high performance by

completing integer and FPU operations in parallel.

3.15.1 FPU (Floating Point Unit) Register Set

In addition to the registers described to this point, the FPU

within the CPU provides the user eight data registers

accessed in a stack-like manner, a control register, and a

status register. The CPU also provides a data register tag

word that improves context switching and stack perfor-

mance by maintaining empty/non-empty status for each of

the eight data registers. In addition, registers contain

pointers to (a) the memory location containing the current

instruction word and (b) the memory location containing

the operand associated with the current instruction word

(if any).

3.15.2 FPU Tag Word Register

The CPU maintains a tag word register that is divided into

eight tag word fields. These fields assume one of four val-

ues depending on the contents of their associated data

registers: Valid (00), Zero (01), Special (10), and Empty

(11). Note: Denormal, Infinity, QNaN, SNaN and unsup-

ported formats are tagged as “Special”. Tag values are

maintained transparently by the CPU and are only avail-

able to the programmer indirectly through the FSTENV and

FSAVE instructions. The tag word with tag fields for each

associated physical register, tag(n), is shown in Table 3-39

on page 90.

3.15.3 FPU Status Register

The FPU communicates status information and operation

results to the CPU through the status register. The fields

in the FPU status register are detailed in Table 3-39 on

page 90. These fields include information related to

exception status, operation execution status, register sta-

tus, operand class, and comparison results. This register

is continuously accessible to the CPU regardless of the

state of the Control or Execution Units.

3.15.4 FPU Mode Control Register

The FPU Mode Control Register (MCR) shown in Table 3-

39 on page 90 is used by the GXm processor to specify

the operating mode of the FPU. The MCR register fields

include information related to the rounding mode selected,

the amount of precision to be used in the calculations, and

the exception conditions which should be reported to the

GXm processor using traps. The user controls precision,

rounding, and exception reporting by setting or clearing

appropriate bits in the MCR.

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