GXM datasheet(60/244 Pages) NSC

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Revision 3.1

Processor Programming (Continued)

3.4

ADDRESS SPACES

The GXm processor can directly address either memory

or I/O space. Figure 3-2 illustrates the range of addresses

available for memory address space and I/O address

space. For the CPU, the addresses for physical memory

range between 0000 0000h and FFFFFFFFh (4 GBytes).

The accessible I/O addresses space ranges between

00000000h and 0000 FFFFh (64 KB). The CPU does not

use coprocessor communication space in upper I/O space

between 800000F8h and 8000 00FFh as do the 386-style

CPUs. The I/O locations 22h and 23h are used for GXm

processor configuration register access.

3.4.1

I/O Address Space

The CPU I/O address space is accessed using IN and

OUT instructions to addresses referred to as “ports.”The

accessible I/O address space is 64 KB and can be

accessed as 8-bit, 16-bit or 32-bit ports.

The GXm processor configuration registers reside within

the I/O address space at port addresses 22h and 23h and

are accessed using the standard IN and OUT instructions.

The configuration registers are modified by writing the

index of the configuration register to port 22h, and then

transferring the data through port 23h. Accesses to the

on-chip configuration registers do not generate external

I/O cycles. However, each operation on port 23h must be

preceded by a write to port 22h with a valid index value.

Otherwise, subsequent port 23h operations will communi-

cate through the I/O port to produce external I/O cycles with-

out modifying the on-chip configuration registers. Write

operations to port 22h outside of the CPU index range

(C0h-CFh and FEh-FFh) result in external I/O cycles and

do not affect the on-chip configuration registers. Reading

port 22h generates external I/O cycles.

I/O accesses to port address range 3B0h through 3DFh

can be trapped to SMI by the CPU if this option is enabled

in the BC_XMAP_1 register (see SMIB, SMIC, and SMID

bits in Table 4-10 on page 101). Figure 3-2 illustrates the

I/O address space.

3.4.2

Memory Address Space

The processor directly addresses up to 4 GB of physical

memory even though the memory controller addresses

only 1 GB of DRAM. Memory address space is accessed

as bytes, words (16 bits) or DWORDs (32 bits). Words

and DWORDs arestoredinconsecutive memory bytes

with the low-order byte located in the lowest address. The

physical address of a word or DWORD is the byte address

of the low-order byte.

The processor allows memory to be addressed using nine

different addressing modes. These addressing modes are

used to calculate an offset address, often referred to as an

effective address. Depending on the operating mode of

the CPU, the offset is then combined, using memory man-

agement mechanisms, into a physical address that is

applied to the physical memory devices.

Memory management mechanisms consist of segmenta-

tion and paging. Segmentation allows each program to

use several independent, protected address spaces. Pag-

ing translates a logical address into a physical address

using translation lookup tables. Virtual memory is often

implemented using paging. Either or both of these mecha-

nisms can be used for management of the GXm proces-

sor memory address space.

Figure 3-2. Memory and I/O Address Spaces

Physical

Memory Space

Accessible

Programmed

I/O Space

FFFFFFFFh

0000FFFFh

00000000h

FFFFFFFFh

00000000h

Physical Memory

4GB

Not

Accessible

64 KB

CPU General

Configuration

Space

00000023h

00000022h

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