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Revision 3.1

Processor Programming (Continued)

3.9

PAGING MECHANISM

The paging mechanism translates a linear address to its

corresponding physical address. If the required page is

not currently present in RAM, an exception is generated.

When the operating system services the exception, the

required page can be loaded into memory and the instruc-

tion restarted. Pages are either 4 KB or 1 MB in size. The

CPU defaults to 4 KB pages that are aligned to 4 KB

boundaries.

A page is addressed by using two levels of tables as illus-

trated in Figure 3-8. Bits[31:22] of the 32-bit linear

address, the Directory Table Index (DTI) are used to

locate an entry in the page directory table. The page

directory table acts as a 32-bit master index to up to 1 K

individual second-level page tables. The selected entry in

the page directory table, referred to as the directory table

entry (DTE), identifies the starting address of the second-

level page table. The page directory table itself is a page

and is,therefore, aligned toa4KB boundary.The physi-

cal address of the current page directory table is stored in

the CR3 control register, also referred to as the Page

Directory Base Register (PDBR).

Figure 3-8. Paging Mechanism

Directory Table Index

(DTI)

Page Table Index

(PTI)

Page Frame Offset

(PFO)

22 21

12 11

Linear

Address

DTE Cache

2-Entry

Fully Associative

Main TLB

32-Entry

4-Way Set

Associative

DTE

4KB

PTE

4KB

Physical Page

4GB

-4 KB

-0

External Memory

Directory Table

Page Table

Memory

CR3

Control

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