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Revision 3.1

Integrated Functions (Continued)

4.3.5

Address Translation

The memory controller supports two address translations

depending on the method used to interleave pages.

4.3.5.1

High Order Interleaving

High Order Interleaving (HOI) uses the most significant

address bits to select which bank the page is located in.

This has the effect of allowing any mixture of DIMM types.

However, it spreads the pages over wide address ranges.

For example, two 8 MB DIMMs contain a total of four com-

ponent pages. Two pages are together in one DIMM sepa-

rated from the other two pages by 8 MB.

4.3.5.2

Low Order Interleaving

Low Order Interleaving (LOI) uses the least significant bits

after the page bits to select which bank the page is

located in. This requires that memory is a power of 2, that

the number of banks is a power of 2, and that the page

sizes are the same. In other words, the DIMMs have to be

of the same type. However, LOI does give a good benefit

by providing a moving page throughout memory. Using

the same example as above, two banks would be on one

DIMM andthe next twobanks wouldbeonthe second

DIMM, but they would be linear in address space. For an

eight bank system that has 1 KB address (8 KB data)

pages, there would be an effective moving page of 64 KB

of data.

4.3.5.3

Physical Address to DRAM Address

Conversion

Auto LOI is in effect whenever the two DIMMs have the

same number of DIMM banks, component banks, module

sizes and page sizes.

Tables 4-17 and Table4-18onpage 113giveAutoLOI

address conversion examples when two DIMMs of the

same size are used in a system. Table 4-17 shows a one

DIMM bank conversion example, while Table 4-18 shows

a two DIMM bank example.

Table 4-19 and Table 4-20 on page 114 give Non-Auto LOI

address conversion examples when either one or two

DIMMs of different sizes are used in a system. Table 4-19

shows a one DIMM bank address conversion example,

while Table 4-20 shows a two DIMM bank example. The

addresses are computed on a per DIMM basis.

Since the DRAM interface is 64 bits wide, the lower three

bits of the physical address get mapped onto the

DQM[7:0] lines. Thus, the address conversion tables

(Tables 4-17 through 4-20) show the physical address

starting from A3.

10:0

GBADD

Graphics Base Address: This field indicates the graphics memory base address, which is program-

mable on 512 KB boundaries. This field corresponds to address bits [29:19].

Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.

GX_BASE+8418h-841Bh

MC_DR_ADD (R/W)

Default Value = 00000000h

31:10

RSVD

Reserved: Set to 0.

9:0

DRADD

Dirty RAM Address: This field is the address index that is used to access the Dirty RAM with the

MC_DR_ACC register. This field does not auto increment.

GX_BASE+841Ch-841Fh

MC_DR_ACC (R/W)

Default Value = 0000000xh

31:2

RSVD

Reserved: Set to 0.

Dirty Bit: This bit is read/write accessible.

Valid Bit: This bit is read/write accessible.

Table 4-16. Memory Controller Registers (Continued)

Bit

Name

Description

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