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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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GXM 데이터시트(PDF) 209 Page - National Semiconductor (TI) |
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GXM 데이터시트(HTML) 209 Page - National Semiconductor (TI) |
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209 / 244 page  Revision 3.1 209 www.national.com Instruction Set (Continued) 9.2.1.3 CPUID Instruction with EAX = 00000002h Standard function 02h (EAX = 02h) of the CPUID instruc- tion returns information that is specific to the National Semiconductor family of processors. Information about the TLB is returned in EAX as shown in Table 9-20. Infor- mation about the L1 cache is returned in EDX. Table 9-19. EDX CPUID Data Returned when EAX = 1 EDX Returned Contents* Feature Flag CR4 Bit EDX[0] 1 FPU On-Chip - EDX[1] 0 Virtual Mode Extension - EDX[2] 0 Debug Extensions - EDX[3] 0 Page Size Extensions - EDX[4] 1 Time Stamp Counter 2 EDX[5] 1 RDMSR / WRMSR Instructions - EDX[6] 0 Physical Address Extensions - EDX[7] 0 Machine Check Exception - EDX[8] 1 CMPXCHG8B Instruction - EDX[9] 0 On-Chip APIC Hardware - EDX[10] 0 Reserved - EDX[11] 0 SYSENTER / SYSEXIT Instructions - EDX[12] 0 Memory Type Range Registers - EDX[13] 0 Page Global Enable - EDX[14] 0 Machine Check Architecture - EDX[15] 1 Conditional Move Instructions - EDX[16] 0 Page Attribute Table - EDX[22:17] 0 Reserved - EDX[23] 1 MMX Instructions - EDX[24] 0 Fast FPU Save and Restore - EDX[31:25] 0 Reserved - Note: *0 = Not supported Table 9-20. Standard CPUID with EAX = 00000002h Register Returned Contents Description EAX xxxx 70xxh TLBis32Entry, 4-way set asso- ciative, and has 4 KByte Pages EAX xx xx xx 01h The CPUID instruction needs to be executed only once with an input value of 02h to retrieve complete information about the cache and TLB EBX Reserved ECX Reserved EDX xx xx xx 80h L1 cache is 16 KBytes, 4-way set associated, and has 16 bytes per line. |
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