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MT9072AB 데이터시트(PDF) 152 Page - Zarlink Semiconductor Inc |
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MT9072AB 데이터시트(HTML) 152 Page - Zarlink Semiconductor Inc |
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152 / 275 page ![]() MT9072 Data Sheet 152 Zarlink Semiconductor Inc. 2F0EM (0) Framer 0 Elastic Mask. This is the mask bit for the F0EVS status bit in the Interrupt Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 1F0RM (0) Framer 0 Rx Line Mask. This is the mask bit for the F0RVS status bit in the Interrupt Vector Register(address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 0F0SM (0) Framer 0 Sync and Overflow Mask. This is the mask bit for the F0SVS status bit in the Interrupt Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. Bit Name Functional Description 15 F7HM (0) Framer 7 HDLC Mask. This is the mask bit for the F7HVS status bit in the Interrupt Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 14 F7EM (0) Framer 7 Elastic Mask. This is the mask bit for the F7EVS status bit in the Interrupt Vector Register(address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 13 F7RM (0) Framer 7 Rx Line Mask. This is the mask bit for the F7RVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 12 F7SM (0) Framer 7 Sync and Overflow Mask. This is the mask bit for the F7SVS status bit in the Interrupt Vector Register(address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 11 F6HM (0) Framer 6 HDLC Mask. This is the mask bit for the F6HVS status bit in the Interrupt Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 10 F6EM (0) Framer 6 Elastic Mask. This is the mask bit for the F6EVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. 9F6RM (0) Framer 6 Rx LineMask. This is the mask bit for the F6RVS status bit in the Interrupt Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will function normally. Table 122 - Interrupt Vector 2 Mask Register (Address 903) (T1) Bit Name Functional Description Table 121 - Interrupt Vector 1 Mask Register (Address 902) (T1) |
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