MT9072AB datasheet(188/275 Pages) ZARLINK

188 / 275 page

MT9072

Data Sheet

188

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

SLC15

SLC14

SLC13

SLC12

SLC11

SLC10

SLC9

SLC8

SLC7

SLC6

SLC5

SLC4

SLC3

SLC2

SLC1

SLC0

Loss of Basic Frame Synchronization Counter. These bits make up a counter which is

incremented for each 125 us period in which basic frame synchronization (BSYNC=1

status register address Y10) is lost. This counter is cleared by a basic frame

synchronization to a loss of basic frame synchronization state transition (BSYNC=0 to 1),

or with an overflow, a RESET (RESET pin or RST bit), or it may be set by writing the

desired value to it. SLC0 is the least significant bit (LSB).

Table 159 - Loss of Basic Frame Synchronization Counter with Auto Clear (R/W Address Y16) (E1)

Bit

Name

Functional Description

EEC15

EEC14

EEC13

EEC12

EEC11

EEC10

EEC9

EEC8

EEC7

EEC6

EEC5

EEC4

EEC3

EEC2

EEC1

EEC0

E-bit Error Counter. These bits make up a counter which is incremented for each

received PCM30 CRC-4 submultiframe E-bit error. This counter is cleared with an

overflow, a RESET (RESET pin or RST bit), or may be set by writing the desired value to

it. EEC0 is the least significant bit (LSB).

Table 160 - E-bit Error Counter (R/W Address Y17) (E1)

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